High speed semiconductor memory apparatus including circuitry to

Details High speed semiconductor memory apparatus including circuitry to High speed semiconductor memory apparatus including circuitry to

1997-08-06

2000-07-18

Nelms, David

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, 365220, 36523005, G11C 1100

Patent

active

06091629&

ABSTRACT:
A semiconductor memory apparatus with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

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patent: 5675529 (1997-10-01), Poole
Hanchek et al., "Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs," Ninth International Conference on VLSI Design, Jan., 1996.
N. Kushiyama et al., "A 295 MHz CMOS 1M (x256) Embedded SRAM Using Bi-directional Read/Write Shared Sense Amps and Self-Timed Pulsed Word-Line Drivers", ISSCC Digest of Technical Papers, pp. 304-305, Feb. 1995.
IEEE Journal of Solid State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1048-1053.
K. Osada et al., "A 2ns Access, 285MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs", ISSCC Digest of Technical Papers, pp. 402-403.

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