Hardened memory cell

Details Hardened memory cell Hardened memory cell

2011-08-02

2011-08-02

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S129000, C365S154000, C365S244000, C257S288000, C438S284000

Reexamination Certificate

active

07990759

ABSTRACT:
The memory cell comprises first and second inverter circuits, connected in a loop. First and second decoupling transistors, normally turned off outside the write phases, are respectively connected between an output of the second inverter circuit and first and second inputs of the first inverter circuit. The memory cell is thereby protected against transient disturbances due to ionizing particles. The gates of the decoupling transistors are preferably respectively connected to a supply voltage for the P-type decoupling transistors and grounded for the N-type decoupling transistors.

REFERENCES:
patent: 5525923 (1996-06-01), Bialas, Jr. et al.
patent: 5631863 (1997-05-01), Fechner et al.
patent: 2004/0124876 (2004-07-01), Plants
patent: 2004/0165417 (2004-08-01), Lesea
patent: 2007/0103966 (2007-05-01), Plants
patent: WO 01/10026 (2001-02-01), None

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