High density planar SRAM cell with merged transistors

Details High density planar SRAM cell with merged transistors High density planar SRAM cell with merged transistors

1998-05-13

2000-10-03

Mai, Son

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 365175, G11C 1100, G11C 1136

Patent

active

061282162

ABSTRACT:
Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes gates which are pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.

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