Architecture for a dual-bank page mode memory with redundancy

Architecture with multi-instance redundancy implementation

Architecture, system and method for compressing repair data...

Area efficient global row redundancy scheme for DRAM

Arrangement for the automatic reconfiguration of an intact equip

Arrangement of redundant cell array for semiconductor memory dev

Arrangement with a memory for storing data

Array architecture and operating methods for digital...

Array block level redundancy with steering logic

Array redundancy supporting multiple independent repairs

Bipolar-transistor type random access memory device having redun

Bipolar-transistor type random access memory having redundancy c

Bipolar-transistor type semiconductor memory device having redun

Block decoding circuits of semiconductor memory devices and...

Block redundancy for memory array

Block redundancy implementation in heirarchical RAM's

Block redundancy implementation in hierarchical rams

Block redundancy in ultra low power memory circuits

Block redundancy in ultra low power memory circuits

Built-in redundancy architecture for computer memories