Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1985-08-29
1988-04-19
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
365210, 371 11, G11C 702, G11C 700, H04L 504, H04J 1500
Patent
active
047394986
ABSTRACT:
An arrangement switches from a defective device of a multi-device system to a redundant duplicate device by assigning a non-volatile memory to each device. Each memory has a single read line to a logic circuit that turns on a device or its duplicate depending upon the memory status. An error detector monitors the devices to activate appropriate memory circuits and logic circuits upon detection of a defect in a particular device.
REFERENCES:
patent: 4345319 (1982-08-01), Bernardini et al.
patent: 4506364 (1985-03-01), Aichelman, Jr. et al.
Satya et al., "Electronic Reorganization of Memory for Handling Uncorrectable Memory Errors", vol. 22, No. 12, IBM Technical Disclosure Bulletin, pp. 5378-5380.
Fears Terrell W.
Koval Melissa J.
Messerschmitt-Bolkow-Blohm GmbH
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