Arrangement of redundant cell array for semiconductor memory dev

Details Arrangement of redundant cell array for semiconductor memory dev Arrangement of redundant cell array for semiconductor memory dev

1992-04-13

1994-10-11

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 371 102, G11C 700

Patent

active

053553373

ABSTRACT:
In a semiconductor memory device having a normal memory cell array which includes repeating arrangements of a predetermined data arrangement and whose data is input and output in response to a column select line signal, an arrangement of a redundant cell array is disclosed. The arrangement has the same data arrangement as the minimally repeated unit of said normal memory cell array, wherein the data is in the redundant cell array input and output in response to a redundant column select line signal. According to the arrangement of the redundant cell array, the reliability and yield of the semiconductor memory device are enhanced.

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