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Technique for reconfiguring a high density memory

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Techniques for reducing redundant element fuses in a dynamic ran

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Testing and evaluation of a semiconductor memory containing redu

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Testing arrangement for a DRAM with redundancy

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Thin film magnetic memory device having redundancy repair...

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Timing fuse option for row repair

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Topography correction for testing of redundant array elements

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Tracking circuit for a memory device

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Trap and patch system for virtual replacement of defective...

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Twisted bit-line compensation for DRAM having redundancy

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Two speed recirculating memory system using partially good compo

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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