Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-06-21
2004-03-30
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230080
Reexamination Certificate
active
06714467
ABSTRACT:
FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
[Not Applicable].
BACKGROUND OF THE INVENTION
One embodiment of the present invention relates to a programmable device for increasing memory cell and memory architecture design yield. More specifically, one embodiment of the present invention relates to block redundancy adapted to increase design yield in memory architecture.
Memory architectures typically balance power and device area against speed. High-performance memory architectures place a severe strain on the power and area budgets of the associated systems, particularly where such components are embedded within a VLSI system, such as a digital signal processing system for example. Therefore, it is highly desirable to provide memory architectures that are fast, yet power- and area-efficient.
Highly integrated, high performance components, such as memory cells for example, require complex fabrication and manufacturing processes. These processes may experience unavoidable parameter variations which may impose physical defects upon the units being produced, or may exploit design vulnerabilities to the extent of rendering the affected units unusable, or substandard.
In memory architectures, redundancy may be important, as a fabrication flaw or operational failure in the memory architecture may result in the failure of that system. Likewise, process invariant features may be needed to insure that the internal operations of the architecture conform to precise timing and parameter specifications. Lacking redundancy and process invariant features, the actual manufacturing yield for particular memory architecture may be unacceptably low.
Low-yield memory architectures are particularly unacceptable when embedded within more complex systems, which inherently have more fabrication and manufacturing vulnerabilities. A higher manufacturing yield of the memory cells may translate into a lower per-unit cost, while a robust design may translate into reliable products having lower operational costs. Thus, it is highly desirable to design components having redundancy and process invariant features wherever possible.
The aforementioned redundancy aspects of the present invention may can render the hierarchical memory structure less susceptible to incapacitation by defects during fabrication or operation, advantageously providing a memory product that is at once more manufacturable, cost-efficient, and operationally more robust.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
SUMMARY OF THE INVENTION
The present invention relates to a system and method for providing redundancy in a hierarchically partitioned memory, by replacing small blocks in such memory for example. One embodiment provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. Such block redundancy scheme, in accordance with the present invention, does not incur excessive access time or area overhead penalties, making it attractive where the memory subblock size is small.
One embodiment of the present invention provides a hierarchal memory structure, comprising at least one active predecoder adapted to be shifted out and at least one redundant predecoder adapted to be shifted in.
One embodiment of the present invention relates to a hierarchical memory structure comprising a synchronously controlled global element, a self-timed local element, and one or more predecoders. In one embodiment, the local element is adapted to interface with the synchronously controlled global element. In such embodiment, at least one predecoder is adapted to fire for current predecoding and at least one predecoder is adapted to fire for previous predecoding. It is further contemplated that a redundant block is adapted to communicate with at least one predecoder.
Another embodiment of the present invention provides a predecoder block used with a hierarchical memory structure, comprising a plurality of active predecoder adapted to fire for current predecoding and at least one redundant predecoder adapted to fire for previous predecoding. The structure further includes a plurality of higher address predecoded lines and a plurality of lower address predecoded lines, wherein one higher address predecoded line is coupled to all the lower address predecoded lines. At least one shift pointer is included, adapted to shift in the redundant predecoder.
Yet another embodiment of the present invention provides a predecoder block used with a hierarchical memory structure. The memory structure comprises at least one current predecoder adapted to fire for current address mapping, at least one redundant predecoder adapted to fire for previous address mapping; and shift circuitry adapted to shift the active predecoder out and the redundant predecoder in.
Yet another embodiment relates to a method of providing redundancy in a memory structure. In this embodiment, the method comprises shifting out a first predecoder block; and shifting in a second predecoder block. It is further contemplated that shifting predecoded lines and shifting circuitry may be coupled to the first and second predecoder blocks.
Other aspects, advantages and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawing, wherein like numerals refer to like parts.
REFERENCES:
patent: 5822268 (1998-10-01), Kirihata
patent: 6411557 (2002-06-01), Terzioglu et al.
patent: 6424554 (2002-07-01), Kawasumi
patent: 6462993 (2002-10-01), Shinozaki
patent: 6532181 (2003-03-01), Saito et al.
Afghahi Cyrus
Terzioglu Esin
Winograd Gil I.
McAndrews Held & Malloy Ltd.
Nguyen Tan T.
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