Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1985-10-17
1988-05-10
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
365230, G11C 700
Patent
active
047440600
ABSTRACT:
A semiconductor memory device of a bipolar-transistor type including a memory cell array, a redundancy array, a defective address memory circuit for storing a defective address and a comparing circuit for comparing an input address with the defective address. The defective address memory circuit includes a plurality of information memory circuits. The information memory circuits include a plurality of diode stages for determining their output amplitudes. When an input address coincides with the defective address stored in the address memory circuit, the redundancy array is selected instead of the memory cell array.
REFERENCES:
patent: 4365319 (1982-12-01), Takemae
patent: 4399372 (1983-08-01), Tanimoto et al.
patent: 4592024 (1986-05-01), Sakai et al.
Fujitsu Limited
Popek Joseph A.
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