Architecture for a dual-bank page mode memory with redundancy

Details Architecture for a dual-bank page mode memory with redundancy Architecture for a dual-bank page mode memory with redundancy

2000-10-02

2001-10-30

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S063000, C365S196000, C365S230060

Reexamination Certificate

active

06310805

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor memory circuits. More particularly, the present invention relates to an architecture for a dual-bank page mode memory with redundancy.
Semiconductor memory circuits provide storage of large amounts of data and ready access to stored data A memory circuit consists of an array of core cells. Each core cell stores one or more bits of data. The core cells are each individually addressable by a unique combination of address inputs to the memory circuit. The address circuits are located in the periphery of the memory circuit, along with sense amplifiers which detect the logical state of the data in an addressed core cell. The sense amplifiers provide the detected data to an I/O circuit for external communication. A row address is provided along a word line and a column address is provided to the sense amplifiers to select the proper bit line of the addressed core cell. In some technologies, the data in the core cells may be written as well as read by peripheral circuits of the memory.
Semiconductor memories provide a large number of features to enhance convenience for the user. Page mode operation has been developed to reduce read access times by accessing a page of data from the core cell array and reading the data from the accessed page. Page access time to read the data from the page may be as little as one-third the initial access time needed to read the data from the core cell array. Dual-bank memories permit simultaneous read and write operations. In such memories, the host system can program data in one bank, then immediately and simultaneously read from the other bank, with zero latency between the read and write operations. Another convenience feature is byte-wide or word-wide data input/output circuits, in which eight bits or 16 bits of data are written or read by the memory circuit at one time.
To reduce manufacturing defects and improve the manufacturing yield for semiconductor memories, redundant designs have been developed to replace defective bits in the core cell array. The array is designed with additional redundant core cells which may be switched in to take the place of a defective core cell. In addition, redundant sense amplifiers are included to detect the data stored in the redundant core cells and provide the data to an output circuit.
In conventional redundancy circuits, when a defective core cell must be replaced, an entire redundant byte or word is switched into the circuit. This is done instead of switching a single redundant bit to replace the single failing bit at one I/O circuit of the byte or word selected. Thus, other bit lines of the same address, different I/O circuit, will be replaced even though they don't have defects. This is wasteful of area or real estate on the memory circuit. However, this conventional technique simplifies the circuit design and the wasted area can be made negligible if the memory is not a page mode design. Conventional redundancies are based on sectorization of the memory.
In page mode designs, however, the wiring interconnections necessary to implement redundancy become significant. Moreover, if a dual-bank capability is added to the page mode design, an area-efficient design is not readily available for implementing redundancy on the memory circuit
Accordingly, there is a need for an improved memory circuit which provides the advantages of redundant core cells with the convenience of page mode operation and with dual-bank design.
BRIEF SUMMARY OF THE INVENTION
By way of introduction only, a memory circuit in accordance with the present invention provides redundancy in a page mode device configured as a dual-bank memory. The memory circuit includes an array of core cells including redundant core cells. Sense amplifiers are associated with each column of core cells and redundant core cells. Word selection circuitry couples sense amplifiers to input/output (I/O) buffers of the memory circuit on an I/O-by-I/O basis. Any bit of any word on a page can be individually replaced by the word selection circuitry.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation of the following claims, which define the scope of the invention.


REFERENCES:
patent: 5349558 (1994-09-01), Cleveland et al.
patent: 5748561 (1998-05-01), Hotta
patent: 5784321 (1998-07-01), Yamamura
patent: 6094381 (2000-07-01), Isa
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AMD publication titled, “3.0 Volt-only Page Mode Flash Memory Technology”, Technology Background, AMD Publication, dated Oct. 1998, pp 1-7.
AMD publication titled, “Am29DL400B 4 Megabit (512 K × 8-Bit/256 K × 16-Bit) CMOS 3.0 Volt-only, Simultaneous Flash Memory”, AMD Publication No. 21606, dated Mar. 23, 1999, pp 1-41.
U.S.applicationl No. 09/676,623 Filed: Oct. 2, 2000—Copy of application as filed in the PTO enclosed.

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