Area efficient global row redundancy scheme for DRAM

Details Area efficient global row redundancy scheme for DRAM Area efficient global row redundancy scheme for DRAM

1999-07-22

2000-08-08

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

365 63, G11C 700

Patent

active

06101138&

ABSTRACT:
In this invention a global row redundancy scheme for a DRAM is described which effectively uses the resources of the chip to produce an area efficient design. The DRAM is constructed from two types of memory blocks, one that has a redundant cell array and one that does not. Both memory block types contain a memory cell array and bit line sense amplifiers. The bit line sense amplifiers, contained on the block with the redundant cell array, are shared with the memory cell array also contained in the block, and thus eliminating the need for sense amplifiers for use only with the redundant cell array. Although, every block could contain a redundant cell array, only one or two blocks with the redundant cell array are normally used. In the global row redundancy scheme repair can be made to any row containing a failed memory cell located in any memory block by using any unused rows in any redundant cell array, and in doing so provides a maximum effectiveness in repairing DRAM's that provides the opportunity to maximize yield.

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Kirihata et al., "Fault-Tolerant Designs for 256 Mb DRAM", IEEE Journal of Solid State Circuits, vol. 31, No. 4, Apr. 1996, pp. 559-566.

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