Built-in redundancy architecture for computer memories

Details Built-in redundancy architecture for computer memories Built-in redundancy architecture for computer memories

2000-04-26

2001-04-24

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060, C365S230030, C365S230010

Reexamination Certificate

active

06222783

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to architectures for computer memories, and in particular to the architecture of computer memories provided with a main memory and a spare memory.
BACKGROUND OF THE INVENTION
Computer memories, such as static random access memories (SRAMs), include large arrays of physical memory cells. In the manufacture of chips bearing large arrays of physical memory cells, a very large percentage, if not all, of the chips will have a defect in at least one of the memory cells. A defect in at least one of the cells is unacceptable. In the past, for SRAMs, it has been impractical to discard all but those chips that contain no defective cells. In DRAMs, which are generally much larger arrays, discarding all chips with defects results in unacceptably low yields. As a result, memories are manufactured with both a main memory and a spare memory. The spare memory is specifically provided to replace defective memory cells in the main memory.
In a conventional memory, all of the cells on a single chip are disposed in a single block memory array. Devices for accessing the cells are arranged on two sides of the block memory array. For example,
FIG. 1
depicts a prior art memory
10
including block memory array
12
. Memory
10
may be a 64 K memory having 512 rows by 128 columns of cells. The rows are selected by block row decoders
14
, physically located on one side of block memory array
12
, adjacent the ends of the row lines. Each row line is electrically connected to block row decoders so that appropriate signals can be received and transmitted. The columns arc connected to 8 input/outputs through a series of devices. At the end of each column line, there are line precharges
16
, corresponding in size, in bits, to the number of columns. Physically adjacent line precharges
16
, and appropriately electrically connected, are read/write multiplexers
18
. In the example of
FIG. 1
, with a block memory array
12
having 128 columns, there are eight 16 channel read/write multiplexers
18
. Adjacent read/write multiplexers
18
are column decoders
19
and read/write circuits
20
, which are electrically connected to input/outputs (not shown). Block controls
22
are located along an edge of the line precharges, the multiplexers, and the column decoders and read/write circuits, and along an edge of the block row decoders, to provide appropriate controls.
Conventionally, when a bad cell is detected, physical connections are laser burned for the row and column lines from the bad cell to a cell in a spare memory block.
In an application filed simultaneously herewith, a method and system have been developed for avoiding the need for creating physical connections. Rather, a look up table is maintained with the address of each bad cell, and a corresponding address of the corresponding cell in the spare memory block.
SUMMARY OF THE INVENTION
In one aspect of the invention, there is provided a computer memory having a selected number of main memory cells, which memory cells are located on a single substrate but in a plurality of physically separated arrays. Each array has associated with it an array of spare memory cells. The array of spare memory cells is located adjacent to its associated main memory cell array. In particular, the rows in the spare memory cell array are aligned with the rows in the associated main memory cell array. The main memory blocks are divided into subblocks. Within each subblock, all columns are addressed by a single multiplexer unique to that subblock.
In another aspect of the invention, a computer memory has one or more main memory blocks and a spare memory block corresponding to each main memory block. Each main memory block has a main memory input/output bus coupled to the main memory block. A data input bus and a data output bus is provided corresponding to each subblock in the main memory block. Each data input bus and data output bus is electrically coupled to a main memory bus, and each spare memory block. Data can therefore be readily directed either to one of the subblocks in the main memory or to one of the spare memory blocks.


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