Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2006-07-18
2006-07-18
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189020
Reexamination Certificate
active
07079431
ABSTRACT:
An arrangement with a memory for storing data has a first memory for storing data, switching devices which stipulate whether access to the first memory involves output of the data stored in the first memory or other data, and a second memory for storing the other data. The arrangement is distinguished in that it contains a third memory (103, 203, 310), which is addressed by the address (A) which is used to access the first memory or by a portion (AH) of this address and contains information about which data in the first memory are to be replaced with other data.
REFERENCES:
patent: 5438546 (1995-08-01), Ishac et al.
patent: 5708613 (1998-01-01), Creed et al.
patent: 5793683 (1998-08-01), Evans
patent: 6314031 (2001-11-01), Sellmair et al.
patent: 6671834 (2003-12-01), Zhu et al.
patent: 6751138 (2004-06-01), Kuroda et al.
patent: 6862700 (2005-03-01), Zhu et al.
patent: 6868022 (2005-03-01), Scheuerlein et al.
patent: 2003/0076716 (2003-04-01), Paul et al.
patent: 0 392 895 (1990-03-01), None
patent: 0 442 301 (1991-01-01), None
IBM Technical Disclosure Bulletin; vol. 37, No. 06A; “Bit Sparing Logic for Semiconductor Memory Systems”.
Kock Ernst Josef
Mischo Walter
Baker & Botts L.L.P.
Infineon - Technologies AG
Nguyen Van-Thu
LandOfFree
Arrangement with a memory for storing data does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Arrangement with a memory for storing data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arrangement with a memory for storing data will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3566510