Block redundancy in ultra low power memory circuits

Details Block redundancy in ultra low power memory circuits Block redundancy in ultra low power memory circuits

1999-12-15

2001-06-19

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S226000, C365S227000

Reexamination Certificate

active

06249464

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to block redundancy generally and, more particularly, to a block redundancy method and/or architecture that may be used with ultra low power memory circuits.
BACKGROUND OF THE INVENTION
Conventional block redundancy circuits may disconnect defective bitlines from a power supply using either fuses or gated loads. Conventional block redundancy circuits (i) only address standby current related to bitline defects, (ii) do not address defects related to intercell problems and (iii) are costly from a die area point of view.
Referring to
FIG. 1
, a conventional circuit
10
used for block and/or column redundancy is shown. The circuit
10
comprises a fuse
12
and a fuse
14
. The fuses
12
and
14
disconnect defective bitlines BIT and BITB from the power supply of the circuit
10
.
Referring to
FIG. 2
, another conventional circuit
20
used for block redundancy is shown. The circuit
20
comprises a gate
22
, a number of transistors
24
a
-
24
n
and a number of memory cells
26
a
-
26
n
. The transistors
24
a
-
24
n
disconnect defective bitlines BIT and BITB from the power supply of the circuit
20
. The transistors
24
a
-
24
n
are controlled by the gate
22
.
Referring to
FIG. 3
, another conventional circuit
30
for block redundancy is shown. The circuit
30
comprises a transistor
32
, a number of transistors
34
a
-
34
n
and a number of memory cells
36
a
-
36
n
. The transistor
32
supplies power to the circuit
30
. The transistors
34
a
-
34
n
are coupled between the power supply and the bitlines BIT and BITB. The transistors
34
a
-
34
n
control the power supplied to the bitlines BIT and BITB. Transistor
32
disconnects the power supply of circuit
30
from the defective bitlines BIT and BITB.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a memory array and a logic circuit. The memory array may be configured to read or write data in response to (i) one or more enable signals and (ii) a global signal. The logic circuit may be configured to generate the enable signals in response to one or more address signals. De-assertion of the enable signals generally reduces current consumption in the memory array.
The objects, features and advantages of the present invention may include implementing a method and/or architecture that may (i) allow a power supply to be completely decoupled from a memory array, including Vcc, bitlines and their associated wells, (ii) eliminate contribution to standby current caused by memory array defects, (iii) allow the power supply to be decoupled from sub wordline driver, bitline loads and sense amplifiers, (iv) disable operation of block write functions, (v) eliminate contribution of a defective block to operational current, and/or (vi) increase die area efficiency.


REFERENCES:
patent: 5349557 (1994-09-01), Yoshida
patent: 5390150 (1995-02-01), Kwak et al.
patent: 5673231 (1997-09-01), Furutani

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