Block decoding circuits of semiconductor memory devices and...

Details Block decoding circuits of semiconductor memory devices and... Block decoding circuits of semiconductor memory devices and...

2011-07-12

2011-07-12

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060, C365S230030

Reexamination Certificate

active

07978548

ABSTRACT:
A block decoding circuit of a semiconductor memory device includes a plurality of block decoders, a plurality of repair address check circuits, a dummy repair address check circuit and a block selection signal generation circuit. The plurality of block decoders are configured to decode a received block selection address. The plurality of repair address check circuits are configured to generate second output signals based on whether a received block selection address and word line selection address are repair addresses. The dummy repair address check circuit is configured to generate a control signal in response to the block selection address and the word line selection address. The block selection signal generation circuit is configured to generate block selection signals based on the first output signals from the plurality of block decoders, the control signal from the dummy repair address circuit, and the second output signals from the repair address check circuits.

REFERENCES:
patent: 2009/0003118 (2009-01-01), Yoo
patent: 2009/0168570 (2009-07-01), Park
patent: 2001-035184 (2001-02-01), None
patent: 10-1999-0079136 (1999-11-01), None
patent: 10-2000-0045904 (2000-07-01), None
patent: 10-2000-0061317 (2000-10-01), None

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