Array redundancy supporting multiple independent repairs

Details Array redundancy supporting multiple independent repairs Array redundancy supporting multiple independent repairs

2007-04-17

2007-04-17

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030

Reexamination Certificate

active

11330693

ABSTRACT:
Arrays such as SRAMs, DRAMs, CAMs & Programmable ROMs having multiple independent failures are repaired using redundant bit lines. A first embodiment provides redundant bit lines on one side of the array. During a write, data is shifted towards the redundant bit lines on the one side of the array, bypassing failed bit lines. A second embodiment provides a spare bit line on each side of the array. During a write, a first failing bit line is replaced by a first spare bit line on a first side of the array, and a second failing bit line is replaced by a second spare bit line on a second side of the array.

REFERENCES:
patent: 6909647 (2005-06-01), Horiguchi et al.
IBM Patent Application POU920040240US1, U.S. Appl. No. 11/053,812, filed Feb. 9, 2005, “Method and Apparatus for Implementing Multiple Column Redundancy for Memory”, James W. Dawson, et al.

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