Array architecture and operating methods for digital...

Details Array architecture and operating methods for digital... Array architecture and operating methods for digital...

2006-04-25

2006-04-25

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S185200, C365S185220, C365S185290, C365S210130, C365S230030

Reexamination Certificate

active

07035151

ABSTRACT:
Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

REFERENCES:
patent: 5083294 (1992-01-01), Okajima
patent: 5450360 (1995-09-01), Sato
patent: 5914907 (1999-06-01), Kobayashi et al.
patent: 5930169 (1999-07-01), Iwata et al.

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