Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1985-10-17
1988-05-17
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
365189, G11C 1300
Patent
active
047455829
ABSTRACT:
A bipolar-transistor type RAM device, particularly an ECL type RAM device, includes a memory cell array, an address receiving circuit, a normal memory cell selecting circuit, and a redundancy configuration. The redundancy configuration includes a redundancy memory cell array, a defective memory address storing circuit, an address comparing circuit, and a redundancy memory cell selecting circuit. The address comparing circuit directly receives the address signal and the defective memory address signal. The normal memory cell selecting circuit is energized when the address signal does not equal the defective memory address signal. Otherwise, the redundancy memory cell selecting circuit is energized.
REFERENCES:
patent: 4462091 (1984-07-01), Knepper et al.
patent: 4523313 (1985-06-01), Nibby, Jr. et al.
patent: 4577294 (1986-03-01), Brown et al.
Awaya Tomoharu
Fukushi Isao
Fears Terrell W.
Fujitsu Limited
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