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Vertical double gate transistor structure

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Vertical double-channel silicon-on-insulator transistor and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Vertical double-gate field effect transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Vertical DRAM cell with TFT over trench capacitor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Vertical DRAM device with self-aligned upper trench shaping

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Vertical DRAM punchthrough stop self-aligned to storage trench

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Vertical dual gate field effect transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Vertical field effect transistor and manufacturing method thereo

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Vertical field effect transistor and method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
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Vertical field effect transistor with metal oxide as...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Vertical field-effect transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Vertical flash memory cell with buried source rail

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Vertical floating body cell of a semiconductor device and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Vertical floating gate transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Vertical floating gate transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Vertical floating gate transistor with epitaxial channel

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Vertical gain cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Vertical gain cell and array for a dynamic random access...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Vertical gate CMOS with lithography-independent gate length

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Vertical gated access transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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