Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-07-10
2007-07-10
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, C257SE21655
Reexamination Certificate
active
10931545
ABSTRACT:
A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a source region, and a second vertical MOS transistor merged with the sense transistor. Addressing the second vertical MOS transistor provides a means for changing a potential of the floating body of the sense transistor. The vertical gain cell can be used in a memory array with a read data/bit line and a read data word line coupled to the sense transistor, and with a write data/bit line and a write data word line coupled to the second transistor of the vertical gain cell.
REFERENCES:
patent: 4826780 (1989-05-01), Takemoto et al.
patent: 4970689 (1990-11-01), Kenney
patent: 4999811 (1991-03-01), Banerjee
patent: 5006909 (1991-04-01), Kosa
patent: 5017504 (1991-05-01), Nishimura et al.
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5042011 (1991-08-01), Casper et al.
patent: 5066607 (1991-11-01), Banerjee
patent: 5078798 (1992-01-01), Nicolson et al.
patent: 5122986 (1992-06-01), Lim
patent: 5220530 (1993-06-01), Itoh
patent: 5280205 (1994-01-01), Green et al.
patent: 5291438 (1994-03-01), Witek et al.
patent: 5308783 (1994-05-01), Krautschneider et al.
patent: 5329481 (1994-07-01), Seevinck et al.
patent: 5378914 (1995-01-01), Ohzu et al.
patent: 5381302 (1995-01-01), Sandhu et al.
patent: 5385853 (1995-01-01), Mohammad
patent: 5414288 (1995-05-01), Fitch et al.
patent: 5448513 (1995-09-01), Hu et al.
patent: 5478772 (1995-12-01), Fazan
patent: 5506166 (1996-04-01), Sandhu et al.
patent: 5519236 (1996-05-01), Ozaki
patent: 5574299 (1996-11-01), Kim
patent: 5627785 (1997-05-01), Gilliam et al.
patent: 5707885 (1998-01-01), Lim
patent: 5719409 (1998-02-01), Singh et al.
patent: 5732014 (1998-03-01), Forbes
patent: 5793686 (1998-08-01), Furutani et al.
patent: 5854500 (1998-12-01), Krautschneider
patent: 5897351 (1999-04-01), Forbes
patent: 5909618 (1999-06-01), Forbes et al.
patent: 5936274 (1999-08-01), Forbes et al.
patent: 5937296 (1999-08-01), Arnold
patent: 5959327 (1999-09-01), Sandhu et al.
patent: 5966319 (1999-10-01), Sato
patent: 5973356 (1999-10-01), Noble et al.
patent: 5991225 (1999-11-01), Forbes et al.
patent: 5998820 (1999-12-01), Chi
patent: 5999455 (1999-12-01), Lin et al.
patent: 6030847 (2000-02-01), Fazan et al.
patent: 6031263 (2000-02-01), Forbes et al.
patent: 6072209 (2000-06-01), Noble et al.
patent: 6077745 (2000-06-01), Burns, Jr. et al.
patent: 6097065 (2000-08-01), Forbes et al.
patent: 6104061 (2000-08-01), Forbes et al.
patent: 6111286 (2000-08-01), Chi et al.
patent: 6124729 (2000-09-01), Noble et al.
patent: 6143636 (2000-11-01), Forbes et al.
patent: 6150687 (2000-11-01), Noble et al.
patent: 6153468 (2000-11-01), Forbes et al.
patent: 6172390 (2001-01-01), Rupp et al.
patent: 6191448 (2001-02-01), Forbes et al.
patent: 6204115 (2001-03-01), Cho
patent: 6238976 (2001-05-01), Noble et al.
patent: 6246083 (2001-06-01), Noble
patent: 6249020 (2001-06-01), Forbes et al.
patent: 6249460 (2001-06-01), Forbes et al.
patent: 6282115 (2001-08-01), Furukawa et al.
patent: 6307775 (2001-10-01), Forbes et al.
patent: 6316309 (2001-11-01), Holmes et al.
patent: 6350635 (2002-02-01), Noble et al.
patent: 6384448 (2002-05-01), Forbes
patent: 6399979 (2002-06-01), Noble et al.
patent: 6440801 (2002-08-01), Furukawa et al.
patent: 6456535 (2002-09-01), Forbes et al.
patent: 6492233 (2002-12-01), Forbes et al.
patent: 6501116 (2002-12-01), Kisu, deceased et al.
patent: 6504201 (2003-01-01), Noble et al.
patent: 6531730 (2003-03-01), Sandhu et al.
patent: 6538916 (2003-03-01), Ohsawa
patent: 6566682 (2003-05-01), Forbes
patent: 6624033 (2003-09-01), Noble
patent: 6625057 (2003-09-01), Iwata
patent: 6661042 (2003-12-01), Hsu
patent: 6680864 (2004-01-01), Noble
patent: 6686624 (2004-02-01), Hsu
patent: 6710465 (2004-03-01), Song et al.
patent: 6727141 (2004-04-01), Bronner et al.
patent: 6747314 (2004-06-01), Sundaresan et al.
patent: 6750095 (2004-06-01), Bertagnoll et al.
patent: 6781197 (2004-08-01), Fujishima et al.
patent: 6838723 (2005-01-01), Forbes
patent: 6940761 (2005-09-01), Forbes
patent: 6943083 (2005-09-01), Forbes
patent: 6956256 (2005-10-01), Forbes
patent: 6975531 (2005-12-01), Forbes
patent: 7030436 (2006-04-01), Forbes
patent: 7149109 (2006-12-01), Forbes
patent: 7151690 (2006-12-01), Forbes
patent: 2001/0028078 (2001-10-01), Noble
patent: 2001/0030338 (2001-10-01), Noble
patent: 2001/0032997 (2001-10-01), Forbes et al.
patent: 2001/0044188 (2001-11-01), Heo et al.
patent: 2001/0053096 (2001-12-01), Forbes et al.
patent: 2002/0098639 (2002-07-01), Kisu et al.
patent: 2002/0126536 (2002-09-01), Forbes et al.
patent: 2003/0001191 (2003-01-01), Forbes et al.
patent: 2003/0129001 (2003-07-01), Kisu et al.
patent: 2003/0155604 (2003-08-01), Sandhu et al.
patent: 2003/0205754 (2003-11-01), Forbes et al.
patent: 2005/0012130 (2005-01-01), Forbes
patent: 2005/0024936 (2005-02-01), Forbes
patent: 2005/0041457 (2005-02-01), Forbes
patent: 2005/0068828 (2005-03-01), Forbes
patent: 2005/0094453 (2005-05-01), Forbes
patent: 2005/0265069 (2005-12-01), Forbes
patent: 2006/0028859 (2006-02-01), Forbes
patent: 2006/0226463 (2006-10-01), Forbes
patent: 2006/0231879 (2006-10-01), Forbes
patent: 2006/0252206 (2006-11-01), Forbes
patent: 61-140170 (1986-06-01), None
patent: 5226661 (1993-09-01), None
Adler, E., et al., “The Evolution of IBM CMOS DRAM Technology”,IBM Journal of Research&Development, 39(1-2), (Jan.-Mar. 1995), 167-188.
Blalock, T. N., et al., “An Experimental 2T Cell RAM with 7 NS Access Time at Low Temperature”,1990 Symposium on VLSI Circuits, Digest of Technical Papers, (1990), 13-14.
Kim, Wonchan, “A low-voltage multi-bit DRAM cell with a built-in gain stage”,ESSCIRC 93: Nineteenth European Solid-State Circuits Conference. Proceedings, (1993),37-40.
Kim, W., “An Experimental High-Density DRAM Cell with a Built-in Gain Stage”,IEEE Journal of Solid-State Circuits, 29(8), (Aug. 1994),978-981.
Krautschneider, W H., et al., “Fully scalable gain memory cell for future DRAMs”,Microelectronic Engineering, 15(1-4), (Oct. 1991),367-70.
Krautschneider, F., “Planar Gain Cell for Low Voltage Operation and Gigabit Memories”,Symposium on VLSI Technology Digest of Technical papers, (1995),139-140.
Mukai, M., et al., “A novel merged gain cell for logic compatible high density DRAMs”,1997 Symposium on VLSI Technology. Digest of Technical Papers, (Jun. 10-12, 1997),155-156.
Mukai, M , et al., “Proposal of a Logic Compatible Merged-Type Gain Cell for High Density Embedded . . . ”,IEEE Transactions on Electron Devices, (Jun. 1999), 1201-1206.
Ohsawa, T , “Memory design using one-transistor gain cell on SOI”,IEEE International Solid-State Circuits Conference. Digest of Technical Papers, vol. 1, (2002), 152-455.
Okhonin, S , “A SOI capacitor-less 1T-DRAM concept”, 2001 IEEE International SOI Conference. Proceedings,IEEE. 2001, (2000), 153-4.
Rabaey, Jan M., “Digital integrated circuits : a design perspective”, Upper Saddle River, N.J. :Prentice Hall, (1996),585-590.
Rabaey, Jan E., “Digital integrated circuits : a design perspective”,Prentice Hall electronics and VLSI series, Upper Saddle River, N.J. : Prentice Hall, c1996,(1996),585-587.
Shukuri, S , “A complementary gain cell technology for sub-1 V supply DRAMs”, Electron Devices Meeting 1992.Technical Digest, (1992), 1006-1009.
Shukuri, S. , “A Semi-Static Complementary Gain Cell Technology for Sub-1 V Supply DRAMs”,IEEE Transactions on Electron Devices, 41(6), (Jun. 1994),926-931.
Shukuri, S. , “Super-Low Voltage Operation of a Semi-Static Complementary Gain DRAM Memory Cell”, Symposium on VLSI Technology.Digest of Technical Papers, (1993),23-24.
Sunouchi, K , et al., “A self-amplifying (SEA) cell for future high density DRAMs”, International Electron Devices Meeting 1991.Technical Digest, (1991),4
Chaudhari Chandra
Schwegman Lundberg Woessner & Kluth P.A.
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