Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-10-12
2003-01-14
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S157000, C438S212000, C257S302000, C257S329000, C257S401000
Reexamination Certificate
active
06506638
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits (ICs) and methods of manufacturing integrated circuits. More particularly, the present invention relates to a vertical transistor structure and a method of manufacturing integrated circuits having vertical transistors.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large-scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates adjacent a channel region and between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
Generally, conventional ICs have employed lateral transistors or devices. Lateral transistors include source and drain regions disposed below a top surface of a bulk or semiconductor-on-insulator (SOI) substrate and a gate disposed above the top surface. Thus, the source region, drain region, and gate of lateral transistors each consumes valuable space on the top surface of the substrate. The gate is disposed on only one side of a channel between the source and the drain. Accordingly, the conventional lateral device can have a limited drive current.
SOI-type devices generally completely surround a silicon or other semiconductor substrate with an insulator. Lateral devices built on SOI substrates have significant advantages over devices built on bulk-type substrates. The advantages include near ideal subthreshold voltage slope, low junction capacitance, and effective isolation between devices. These advantages lead to further advantages, including reduced chip size or increased chip density, because minimal device separation is needed due to the surrounding insulating layers. Additionally, SOI devices can operate at increased speeds due to reductions in parasitic capacitance.
As demands for integration (transistor density) increase, vertical transistors have been considered. Vertical transistors can be insulated gate field effect transistors (IGFETs), such as, MOSFETS. In a conventional vertical MOSFET, source and drain regions are provided on opposite surfaces (e.g., a top surface and a bottom surface) of a semiconductor layer and a body region is disposed between the source and drain regions. During MOSFET operation, current flows vertically between the source and drain regions through a channel within the body region. The channel is often described in terms of its length, i.e., the spacing between the source and drain regions at the semiconductor surface, and its width, i.e., the dimension perpendicular to the length. Channel width is typically far greater than channel length.
In one example of a conventional vertical FETs on a bulk-type substrate, the bulk-type semiconductor substrate, such as, a silicon substrate, is etched to form trenches or steps. The gate of the vertical transistor is disposed on a side wall of the trench or step, and the channel region is located adjacent to the side wall. Placing a gate conductor in the trench can be a difficult technical feat, especially as the size of gate lengths and gate widths decrease. Due to its small lateral size, the vertical transistor structure generally allows more devices to be contained on a single semiconductor substrate than the conventional lateral structure. Similar to the conventional lateral structure discussed above, the gate conductors of the vertical transistor are disposed on only one side of the channel region, and the current density associated with the vertical FET is accordingly somewhat limited.
As discussed above, vertical transistors offer significant advantages including small wafer surface area consumption due to the vertical nature of the transistor. The vertical nature allows three dimensional integration. In addition, the vertical transistor design is conductive to double gate and surrounded gate structures. Double gate and surrounded gate structures allow an electrical field to be induced in the channel region from two or more sides. Accordingly, the double gate and surrounded gate structures can increase current density and switching speeds. Further, the double gate and surrounded gate structures provide more scalability with respect to controlling short channel effects and can be used to control threshold voltages.
Thus, there is a need for an integrated circuit or electronic device that includes vertical transistors and can be manufactured in an efficient process. Further still, there is a need for vertical transistors having double gate or surrounded gate structures. Even further still, there is a need for a method of manufacturing vertical transistors without providing a gate conductor in a trench. Yet further, there is a need for a method of manufacturing double gate vertical transistors and surrounded gate vertical structures. Yet even further, there is a need for an efficient method of manufacturing a double gate vertical transistor.
SUMMARY OF THE INVENTION
The present invention relates to the method of manufacturing a vertical transistor. The method includes providing a semiconductor substrate including a semiconductor base layer which is below a first insulative layer which is below a semiconductor layer which is below a second insulative layer. The method also includes a providing an aperture through the first insulative layer, the semiconductor layer and the second insulative layer, doping the semiconductor substrate through the aperture, and providing an amorphous semiconductor layer above the second insulative layer and within the aperture.
The present invention further relates to a vertical transistor. The vertical transistor includes a first gate conductor disposed above a top surface of a substrate, a second gate conductor disposed above a top surface of a substrate, a source disposed at least partially below the top surface of the substrate, and a drain disposed entirely above the top surface of the substrate. The first gate conductor is located between two dielectric layers. The second gate conductor is also located between two dielectric layers. A channel region is disposed between the first gate conductor and the second gate conductor and between the drain and the source.
The present invention further relates to a process of forming a vertical transistor having a channel region above a top surface of a substrate. The process includes providing a first dielectric layer, a silicon layer and a second dielectric layer above a top surface of the substrate, providing an aperture in the first dielectric layer, the silicon layer, and the second dielectric layer, forming an amorphous semiconductor layer above the second dielectric layer and within the aperture, doping the amorphous semiconductor layer, and annealing the amorphous semiconductor layer.
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“Ultra-Thin-Body Silicon-On-Insulator MOSFET's for Terabit-Scale Integration” by Yu, Department of Electrical Engineering and Computer Sciences, University of California Berkeley.
Dang Trung
Foley & Lardner
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