Vertical field effect transistor and manufacturing method thereo

Details Vertical field effect transistor and manufacturing method thereo Vertical field effect transistor and manufacturing method thereo

1997-08-19

2000-01-18

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438138, 438192, H01L 218232

Patent

active

060157259

ABSTRACT:
A vertical field effect transistor (1) and a method of manufacturing thereof are disclosed, in which a buried layer (3) of a conduction type opposite to that of a substrate (2) is formed to a predetermined depth in the substrate (2) by ion implantation. The bottom of recess (2a) for forming a protrusion (2b) on the substrate (2) is located within the corresponding one of the buried layer (3). The width of the recess (2a) is set smaller than the width of the buried layer (3). The surface of the protrusion (2b) and the bottom of the recess (2a) are formed with impurities regions (4a, 4b; 5a, 5b) constituting a source and a drain, respectively. A channel length (L) of the channel region formed on the side wall of the protrusion (2b) is defined by the distance between the buried layer (3) and the impurities regions (5a, 5b) on the surface of the protrusion (2b).

REFERENCES:
patent: 4881105 (1989-11-01), Davari et al.
patent: 5380670 (1995-01-01), Hagino
patent: 5424231 (1995-06-01), Yang

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