Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
Patent
1995-06-07
1997-04-29
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having junction gate
H01L 21265, H01L 2124, H01L 2140
Patent
active
056248601
ABSTRACT:
A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The gate (704) may have modulated doping along the channel (706), and the drain (708) may have a lighter doping level than the channel which may be accomplished by an epitaxial overgrowth of the gates (704) to form the channels (706).
REFERENCES:
patent: 4036672 (1977-07-01), Kobayashi
patent: 4712122 (1987-12-01), Nishizawa et al.
patent: 5116455 (1992-05-01), Daly
patent: 5168070 (1992-12-01), Liith
patent: 5231037 (1993-07-01), Yuan et al.
Plumton Donald L.
Yuan Han-Tzong
Brady III W. James
Donaldson Richard L.
Dutton Brian K.
Hoel Carlton H.
Niebling John
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