Vertical double-channel silicon-on-insulator transistor and...

Details Vertical double-channel silicon-on-insulator transistor and... Vertical double-channel silicon-on-insulator transistor and...

2005-11-01

2005-11-01

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S156000, C438S206000, C438S212000, C438S268000

Reexamination Certificate

active

06960507

ABSTRACT:
A vertical double channel silicon-on-insulator (SOI) field-effect-transistor (FET) includes a pair of two vertical semiconductor layers in contact with a pair of parallel shallow trench isolation layers on a substrate, a source, a drain and a channel region on each of the pair of vertical semiconductor layers with corresponding regions on the pair of vertical semiconductor layers facing each other in alignment, a gate oxide on the channel region of both of the pair of the vertical semiconductor layers, and a gate electrode, a source electrode, and a drain electrode electrically connecting the respective regions of the pair of vertical semiconductor layers.

REFERENCES:
patent: 5312782 (1994-05-01), Mayazawa
patent: 6268630 (2001-07-01), Schwank et al.
patent: 6429055 (2002-08-01), Oh
patent: 6515348 (2003-02-01), Hueting et al.
patent: 6706571 (2004-03-01), Yu et al.
patent: 6709982 (2004-03-01), Buynoski et al.
patent: 11-150265 (1999-06-01), None
Choi, et al., “A Spacer Patterning Technology for Nanoscale CMOS”.
IEEE Transactionson Electron Devices, vol. 49, No. 3, pp. 436-441 (Mar. 2002).

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