Vertical field-effect transistor

Details Vertical field-effect transistor Vertical field-effect transistor

2011-08-02

2011-08-02

Fahmy, Wael M (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S268000, C438S286000

Reexamination Certificate

active

07989294

ABSTRACT:
A method produces a vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.

REFERENCES:
patent: 5940707 (1999-08-01), Gardner et al.
patent: 5963061 (1999-10-01), Briner
patent: 6239465 (2001-05-01), Nakagawa
patent: 53067381 (1978-06-01), None
EPO Office Action for Application No. 03 787 593.7 dated Oct. 28, 2010, (9p).

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