Vertical DRAM device with self-aligned upper trench shaping

Details Vertical DRAM device with self-aligned upper trench shaping Vertical DRAM device with self-aligned upper trench shaping

2007-07-24

2007-07-24

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S301000, C257SE27092

Reexamination Certificate

active

11085663

ABSTRACT:
A method and structure for a memory storage cell in a semiconductor substrate includes forming a dopant source material over a lower portion of a deep trench formed in the substrate. An upper portion of the trench is shaped to a generally rectangular configuration, and the dopant source material is annealed so as to form a buried plate of a trench capacitor. The buried plate is self aligned to the shaped upper portion of the trench.

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