Vertical DRAM punchthrough stop self-aligned to storage trench

Details Vertical DRAM punchthrough stop self-aligned to storage trench Vertical DRAM punchthrough stop self-aligned to storage trench

2004-05-03

2004-12-21

Zarneke, David (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S386000

Reexamination Certificate

active

06833305

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a back-to-back, i.e., adjacent, pair of vertical metal oxide semiconductor field effect transistor (MOSFET) trench storage dynamic random access memory (DRAM) cells having a punchthrough stop doping pocket which is centered between two opposing strap outdiffusions. The present invention also provides a method of fabricating the inventive vertical MOSFET trench storage DRAM cells.
BACKGROUND OF THE INVENTION
As the minimum feature size, F, of vertical DRAM arrays is scaled; cell-to-cell interaction becomes an increasing concern. With scaling of a typical prior art 90 nm 8F
2
cell to smaller dimensions, loss of a stored “1” may occur due to cycling of the data stored on an adjacent cell. The cycling wordline and storage node of the adjacent cell drives a non-conservative charge pumping mechanism which is ultimately responsible for loss of a stored “1”.
This dynamic charge loss mechanism can be minimize to some extent by increasing the doping concentration of the array P-well, especially at the depth of the buried-strap outdiffusion. However, to prevent degradation of the retention time tail due to trap assisted junction leakage, the doping concentration adjacent to the strap outdiffusion must be limited
In view of the above-mentioned drawbacks with prior art vertical MOSFFT storage trench DRAM structures, there is a continued need for providing a scaled vertical MOSFET storage trench DRAM structure that has a minimum feature size F of less than about 90 nm, little or no dynamic charge loss, as well as little or no trap assisted junction leakage.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor memory structure having a minimum feature size F of less than about 90 nm.
Another object of the present invention is to provide a scaled semiconductor memory structure wherein the dynamic charge loss mechanism is minimized such that little or no dynamic charge loss is observed.
A further object of the present invention is to provide a scaled memory structure which exhibits little or no trap assisted junction leakage therefore preventing the degradation of the retention time tail.
An even further object of the present invention is to provide a scaled memory structure having punchthrough stop doping pockets that are self-aligned to the storage trenches of the vertical MOSFET DRAM structure.
A still further object of the present invention is to provide a semiconductor memory structure wherein the punchthrough stop doping pockets of the structure share a common mask with the storage trenches of the vertical MOSFET DRAM structure.
These and other objects and advantages are achieved in the present invention by providing a semiconductor memory structure that includes a back-to-back, i.e., adjacent, pair of vertical MOSFET trench storage DRAM cells having a punchthrough stop pocket region of elevated P- or N-well doping which is centered between two opposed strap outdiffusions. In the inventive semiconductor memory structure, the punchthrough stop doping pocket is formed at a location relative to adjacent storage trenches that is independent of alignment tolerances.
Specifically, the inventive semiconductor memory structure comprises:
at least one adjacent pair of trench storage memory cells present in a Si-containing substrate, each memory cell including a vertical transistor overlaying a trench capacitor,
strap outdiffusions present on each vertical sidewall of the trench storage memory cells, wherein said strap outdiffusions interconnect said vertical transistor and said trench capacitor of each memory cell to said Si-containing substrate; and
a punchthrough stop doping pocket located between each adjacent pair of trench storage memory cells, said punchthrough stop doping pocket is centered between said strap outdiffusions.
In embodiments wherein more than one back-to-back pair of trench storage memory cells, i.e., a plurality of adjacently paired trench storage memory cells, are employed, a memory array is formed which includes punchthrough stop doping pockets whose location relative to adjacent storage trenches is independent of alignment tolerance. That is, a memory array is formed wherein the punchthrough doping pockets are located at substantially the same location; including distance from the top surface of the Si-containing substrate as well as distance from storage trenches, within the Si-containing substrate.
Another aspect of the present invention relates to a method of providing the above-mentioned semiconductor memory structure. Specifically, the inventive method comprises the steps of:
(a) forming at least one adjacent pair of trench storage memory cells present in a Si-containing substrate, each memory cell including a vertical transistor overlaying a trench capacitor and strap outdiffusions present on each vertical sidewall of the trench storage memory cells, wherein said strap outdiffusions interconnect said vertical transistor and said trench capacitor of each memory cell to said Si-containing substrate; and
(b) forming a punchthrough stop doping pocket between each adjacent pair of trench storage memory cells, said punchthrough stop doping pocket is centered between said strap outdiffusions and is self-aligned to said trench capacitor.


REFERENCES:
patent: 5731609 (1998-03-01), Hamamoto et al.
patent: 6025224 (2000-02-01), Gall et al.
patent: 6051468 (2000-04-01), Hshieh

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