Vertical flash memory cell with buried source rail

Details Vertical flash memory cell with buried source rail Vertical flash memory cell with buried source rail

2005-04-19

2005-04-19

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S593000

Reexamination Certificate

active

06881628

ABSTRACT:
A non-volatile memory cell has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The control gate is coupled to a word line that is located above the transistor and traverses the memory in a direction perpendicular to the control gate.

REFERENCES:
patent: 5763310 (1998-06-01), Gardner
patent: 5869369 (1999-02-01), Hong
patent: 6265292 (2001-07-01), Parat et al.
patent: 6376312 (2002-04-01), Yu
patent: 6461915 (2002-10-01), Rudeck
patent: 6680508 (2004-01-01), Rudeck
patent: 6717205 (2004-04-01), Gratz

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