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Asymmetric field effect transistor structure and method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Asymmetric gates for high density DRAM

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Asymmetric halo implants

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Asymmetric hetero-doped high-voltage MOSFET (AH 2 MOS)

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Asymmetric MOS technology power device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Asymmetric segmented channel transistors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Asymmetric source/drain junctions for low power silicon on...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Asymmetric-area memory cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Asymmetrical devices for short gate length performance with...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Asymmetrical IGFET devices with spacers formed by HDP...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Asymmetrical MOSFET layout for high currents and high speed...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Asymmetrical MOSFET with gate pattern after source/drain formati

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Asymmetrical p-channel transistor formed by nitrided oxide and l

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Asymmetrical P-channel transistor having a boron migration barri

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Asymmetrical transistor formed from a gate conductor of unequal

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Atomic layer deposited nanolaminates of HfO 2 /ZrO 2 films...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Atomic layer deposited nanolaminates of HfO2/ZrO2 films as...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Atomic layer deposited ZrAl x O y dielectric layers...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Atomic layer deposition of hafnium lanthanum oxides

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Atomic layer deposition of interpoly oxides in a...

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