LandOfFree - US Patents - Listing for Semiconductor device manufacturing: process,Making field effect device having pair of active regions...,Having insulated gate

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Asymmetric gates for high density DRAM

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Asymmetric halo implants

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Asymmetric hetero-doped high-voltage MOSFET (AH 2 MOS)

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Asymmetric MOS technology power device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Asymmetric segmented channel transistors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Asymmetric source/drain junctions for low power silicon on...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Asymmetric-area memory cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Asymmetrical devices for short gate length performance with...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Asymmetrical IGFET devices with spacers formed by HDP...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Asymmetrical MOSFET layout for high currents and high speed...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Asymmetrical MOSFET with gate pattern after source/drain formati

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Asymmetrical p-channel transistor formed by nitrided oxide and l

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Asymmetrical P-channel transistor having a boron migration barri

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Asymmetrical transistor formed from a gate conductor of unequal

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Atomic layer deposited nanolaminates of HfO 2 /ZrO 2 films...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Atomic layer deposited nanolaminates of HfO2/ZrO2 films as...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Atomic layer deposited ZrAl x O y dielectric layers...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Atomic layer deposition of hafnium lanthanum oxides

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Atomic layer deposition of interpoly oxides in a...