Asymmetric field effect transistor structure and method

Details Asymmetric field effect transistor structure and method Asymmetric field effect transistor structure and method

2011-01-05

2011-11-08

Stark, Jarrett (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S329000, C257SE29262, C257SE21410, C257S327000

Reexamination Certificate

active

08053314

ABSTRACT:
Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

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