Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-10-01
1999-04-13
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438532, H01L 21336
Patent
active
058937390
ABSTRACT:
Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
REFERENCES:
patent: 4272881 (1981-06-01), Angle
patent: 4621277 (1986-11-01), Ito et al.
patent: 4855247 (1989-08-01), Ma et al.
patent: 4914046 (1990-04-01), Tobin
patent: 4962054 (1990-10-01), Shikata
patent: 5015598 (1991-05-01), Verhaar
patent: 5066604 (1991-11-01), Chung et al.
patent: 5200358 (1993-04-01), Bollinger et al.
patent: 5286664 (1994-02-01), Horiuchi
patent: 5296398 (1994-03-01), Noda
patent: 5393676 (1995-02-01), Anjum et al.
patent: 5397715 (1995-03-01), Miller
patent: 5525552 (1996-06-01), Huang
patent: 5532176 (1996-07-01), Katada et al.
patent: 5547885 (1996-08-01), Ogoh
patent: 5656518 (1997-08-01), Gardner et al.
patent: 5679592 (1997-10-01), Kang
patent: 5744371 (1998-04-01), Kadosh et al.
patent: 5783458 (1998-07-01), Kadosh et al.
Horiuchi et al., "An Asymmetric Sidewall Process for High Performance LDD MOSFET's," IEEE Transactions on Electron Devices, vol. 41, No. 2, Feb. 1994, pp. 186-190.
Cheek Jon D.
Hause Fred N.
Kadosh Daniel
Advanced Micro Devices , Inc.
Chaudhari Chandra
Daffer Kevin L.
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