Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-06
2001-04-17
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S286000, C438S696000
Reexamination Certificate
active
06218251
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the fabrication of integrated circuits and, more particularly to the fabrication of insulated gate, field effect transistor (IGFET) devices. This invention is related specifically to (IGFET) devices that have source/drain regions having two sub-regions, each sub-region with a different doping level.
2. Description of the Related Art
An insulated gate, field effect transistor (IGFET) device
5
, such as a metal-oxide semiconductor field-effect transistor (MOSFET) is shown in
FIG. 1. A
substrate
10
has a doped well region
12
, a p-doped well region that will be used for purposes of illustration. The substrate
10
has a p-doped channel region
14
that provides a conducting path between the n-doped source/drain region
16
A,
16
B and the n-doped source/drain region
18
A,
18
B. In addition, a p-doped punch-through region
20
, is provided below the channel region
14
. Also formed in the substrate
10
are the isolation structures
22
and
24
. The gate structure of the IGFET device
5
includes a gate dielectric
26
, directly over the channel region
20
, and a gate electrode
28
over the gate dielectric
26
. The gate structure
26
,
28
can include spacers
30
,
32
formed against the walls of the gate structure
26
,
28
. An insulating layer
34
covers the substrate
10
and the gate structure
26
,
28
. The insulating layer
34
has vias formed therein and the vias are filled with a conducting material. The conducting material provides conducting vias
36
to source/drain (electrode) regions
16
A,
16
B and
18
A and
18
B and to the gate electrode
28
. An insulating layer
38
, formed over insulating layer
34
, is patterned and the portions removed as a result of the patterning are filled with conducting material to provide conducting paths
40
. The conducting paths
40
and the remaining insulating material
38
forman interconnect layer providing the electrical coupling between the IGFET device
5
and the remainder of the integrated circuit.
The operation of the IGFET device
5
can be understood as follows. A voltage applied to the gate electrode
28
causes a transverse field in the channel region
14
. The transverse field controls (e.g., modulates) the current flow between source/drain region
16
A,
16
B and source/drain region
18
A,
18
B. The punch-through region
20
is formed to prevent parasitic effects that can occur when this region is not formed in the device
5
. The spacers
30
,
32
and the dual-structured, doped source/drain regions
16
A,
16
B and
18
A,
18
B address a problem generally referred to as the “hot-carrier” effect. When only one source/drain region
16
A and
18
A is present and is formed by doping technique aligned with the electrode structure
26
,
28
, charge carriers from these regions can migrate into the channel region
14
and be trapped by the gate dielectric
26
. These trapped charge carriers adversely affect the transverse electric field normally formed in the channel region
14
by a voltage applied to the gate electrode
28
. The problem is alleviated by lightly-doping source/drain regions
16
A and
18
A using a technique which aligns this doping procedure with the gate structure
26
,
28
. Spacers
30
and
32
are next formed on the walls of the gate structure
26
,
28
. Source/drain regions
16
B and
18
B are formed by a doping procedure, resulting in source/drain doping concentrations at normal levels, that aligns the source/drain regions
16
B and
18
B with the spacers
30
and
32
, respectively. (While this two-level doping procedure effectively eliminates the “hot-carrier” problem, the resistance between the two source/drain dual regions
16
A,
16
B and
18
A,
18
B is increased.) The isolation structures
22
,
24
provide electrical insulation between the device
5
and other areas of the integrated circuit.
In providing the spacers that are used in the fabrication of the two lightly-doped source/drain sub-regions, one representative technique is to use a thick layer of silicon oxide covering the exposed surfaces of the substrate and the gate structure. A greater thickness of silicon oxide will accumulate in a comer region where the gate structure is in contact with the substrate. Thus, when an isotropic etch procedure is performed, the gate structure and the surface of substrate can be exposed while leaving a comer region of silicon oxide, generally referred to as a spacer. This spacer has the ability to prevent the penetration of ions into the substrate and can therefore be used to maintain lightly-doped source/drain regions in the vicinity of the channel regions. However, this procedure has problems associated therewith. Both the rate of formation of the silicon oxide material and the etching rate can be uncertain. This uncertainty can result in spacers having unacceptable thickness or unacceptable geometry. The undesirable properties of the spacers can result in a compromise of the structure of the two regions forming each source/drain region and ultimately in the operation of the device.
SUMMARY OF THE INVENTION
A need has therefore been felt for a technique for the fabrication of IGFET devices which includes the feature that the properties of the spacers can be reproducibly controlled. In addition, a need has been felt for a technique for the fabrication of the devices having the feature that spacers can be formed in a manner that eliminates the need for a two-stage ion implantation process to provide source/drain regions having a lightly-doped sub-region.
The aforementioned and other features are accomplished, according to the present invention, by using, in the fabrication of an IGFET device, a high density plasma (HDP) deposition for the formation of the spacers. The parameters of the high density plasma deposition are sufficiently reproducible so that the geometry and the thickness of the spacers can be determined. Thus, after implantation of the lightly-doped regions aligned with the gate structure, the high density plasma deposition can provide spacers on the wall of the gate structure, which, during the implantation of ions to form the normally-doped source/drain regions, will maintain the integrity of the lightly-doped source/drain region in the vicinity of the channel region. In addition, a device with asymmetrical source/drain regions can be fabricated by forming a mask over a comer region of the gate structure and the substrate. This mask will prevent the formation of a spacer that would normally be associated with one of the device's source/drain regions. During the second source/drain ion implantation, one of the sub-regions doped by the second source/drain ion implantation will be aligned with the spacer while the second source/drain region will be aligned with the gate structure. Because of the controllable parameters of the high density plasma, the spacers formed by this technique can be used to permit the fabrication of an IGFET device with a source/drain region having a lightly-doped portion using a single ion implantation step. The spacer formed using the high density plasma technique will attenuate the normal implantation of ions in such a manner that the source/drain region proximate the channel region will receive the equivalent of an ion implantation doping level used for the lightly-doped source/drain regions.
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patent: 5728621 (199
Gardner Mark I.
Kadosh Daniel
Advanced Micro Devices , Inc.
Elms Richard
Odozynski John A.
Pyonin Adam
Skjerven Morrill & MacPherson LLP
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