Asymmetrical devices for short gate length performance with...

Details Asymmetrical devices for short gate length performance with... Asymmetrical devices for short gate length performance with...

1999-08-04

2003-04-15

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000, C438S276000, C438S278000, C438S514000, C438S519000, C438S531000

Reexamination Certificate

active

06548359

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a field effect transistor (FET) with an implant within the gate length of the FET and a method of making the FET.
2. Brief Description of the Prior Art
It has been found that there are advantages for an FET to have an implant in the channel region that does not extend from the source to the drain and is aligned to the gate edge. For example, a pocket implant can be used to reduce short channel length effects. Yet, it can be undesirable to have a pocket implant extend into the source/drain (S/D) area because of resulting increased junction capacitance. It has also been found that there are advantages for an FET to have a region of controlling V
T
on the source side of the channel with a more conductive V
T
on the drain side. The short effective channel length and low source resistance of such an FET results in increased drive current and the reduced influence of the drain provides superior short channel characteristics. In the prior art, angled implants and lateral diffusions have been used to obtain channel impurity profiles self-aligned to the gate edge. However, these approaches have disadvantages resulting from restrictions in the channel implant profiles that can be obtained and from the interdependence of the channel profile and the S/D extension profiles. It is therefore apparent that transistors having an independent channel implant region that is self aligned to the S/D edge is highly desirable.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a technique for fabrication of FET devices having a well controlled implant region between the two source/drain regions, self aligned to the S/D edge as well as the FET itself. In one embodiment, this implant region is used to create a controlling V
T
region of shorter effective length than the S/D spacing. Preferably, the controlling V
T
region is on the source side of the space between source and drain. In a second embodiment, the implant region is a pocket implant with limited extension into the S/D region. In a third embodiment, the implant is a S/D extension implant with extension into the channel region being independent of the diffusion of the S/D implant. The term “controlling V
T
region” as used herein refers to that region which is the least conducting region and thus controls the current flow. For an n-channel transistor, this will generally be the more positive (higher) V
T
. The controlling region could have a positive V
T
and the rest of the channel could have a negative V
T
, or the controlling region could have a negative V
T
with the rest of the channel having a more negative V
T
. The same applies for p-channel transistors except for a polarity reversal.
In accordance with the present invention, there is provided a fabrication technique for fabrication of FET devices having a well controlled sub-lithographic effective gate length, independent of gate orientation. The shorter effective channel length provides increased drive current since drive current is inversely proportional to channel length. The shorter effective channel length is achieved without requiring that the physical gate also be as short as the effective channel length. This provides superior short gate length device characteristics and avoids the problems inherent in requiring the shorter gate length during fabrication of the device.
One way to achieve the effective short channel is to use a disposable gate process with masked/disposable sidewalls. This is accomplished by providing a doped substrate having spaced apart source/drain regions with a pad oxide and a patterned mask over the source/drain regions, preferably of silicon nitride, leaving the gate region exposed after disposal of the disposable gate. A removable sidewall is formed on the mask, preferably with silicon nitride, and the remaining gate region between the disposable sidewalls is filled with silicon dioxide with the surface then being planarized, preferably with a chemical mechanical polish (CMP). The sidewall adjacent to the source region is then removed by depositing and patterning a resist over the planarized surface and etching. A high V
T
implant is then performed through the space from which the sidewall was removed to dope the channel region adjacent to the source region. The remaining sidewall is then removed. This is followed by a low V
T
implant in the channel region between the source and drain regions. It should be understood that the high V
T
implant can be a counter doping of the low V
T
implant with appropriate masking to perform the implants in this manner. The result is an effective channel length, L, which is independent of the original disposable gate length. Fabrication then proceeds in standard manner to complete the device.
As a second embodiment, the low V
T
channel implant can be performed initially after removal of the disposable gate and formation of disposable sidewalls on the mask as in the first embodiment, the sidewall on the source side is retained and the sidewall on the drain side is removed with appropriate deposition and patterning of resist and etching. A low V
T
is then provided into the exposed portion of the channel. The remaining sidewall at the source end of the channel is then removed and a high V
T
implant is then provided of opposite conductivity type to the low V
T
implant to provide the same result as in the first embodiment. Fabrication then proceeds in standard manner to complete the device.
As a third embodiment, it is desirable to add a liner over the mask surface, sidewalls and pad oxide prior to fabrication as noted above with reference to the first and second embodiments. The liner is preferably silicon nitride. The liner aids etch selectivity and protects the surface of the silicon when performing the implants.
As a fourth embodiment, the FET can be made symmetrical rather than asymmetrical as described in the first and second embodiments with a different implant in the center of the channel region relative to the source and drain ends of the channel region. An implant can be performed following sidewall formation. The sidewalls would then be removed and the entire channel region would be doped n- or p-type to provide either a less heavily net doped region adjacent the source and drain regions if the same conductivity type dopant is used or a more heavily net doped region adjacent the source and drain if the opposite conductivity type dopant is used. The resist pattern used to mask removal of selected sidewalls can also distinguish n- and p-channel transistors for different V
T
implants. Optionally, an implant can be performed before formation of the sidewalls, followed by an implant after formation of the sidewalls. For this option, the sidewall can be left in place for formation of the actual gate.


REFERENCES:
patent: 4276095 (1981-06-01), Beilstein, Jr. et al.
patent: 4948745 (1990-08-01), Pfiester et al.
patent: 5374574 (1994-12-01), Kwon
patent: 5532175 (1996-07-01), Racanelli et al.
patent: 5548148 (1996-08-01), Bindal
patent: 5736446 (1998-04-01), Wu
patent: 5766969 (1998-06-01), Fulford, Jr. et al.
patent: 5804497 (1998-09-01), Gardner et al.
patent: 5843825 (1998-12-01), Hwang
patent: 5858848 (1999-01-01), Gardner et al.
patent: 5892707 (1999-04-01), Noble
patent: 6096586 (2000-08-01), Milic-strkalj et al.
patent: 6146953 (2000-11-01), Lee et al.
patent: 6228725 (2001-05-01), Nandakumar et al.
G.G. Shahidi et al. “Indium Channel Implant for Improved Short-Channel Behavior of Submicrometer Nmosfet's”, IEE, 1993, pp. 409-411.

Affiliated with

Also associated with

Rating

Asymmetrical devices for short gate length performance with... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Asymmetrical devices for short gate length performance with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asymmetrical devices for short gate length performance with... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3102816