Asymmetric halo implants

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S290000, C438S302000, C438S306000, C438S525000, C438S527000

Reexamination Certificate

active

06916716

ABSTRACT:
Various methods of fabricating halo regions are disclosed. In one aspect, a method of manufacturing is provided that includes forming a symmetric transistor and an asymmetric transistor on a substrate. A first mask is formed on the substrate with a first opening to enable implantation formation of first and second halo regions proximate first and second source/drain regions of the symmetric transistor. First and second halo regions of a first dosage are formed beneath the first gate by implanting off-axis through the first opening. A second mask is formed on the substrate with a second opening to enable implantation formation of a third halo region proximate a source region of the second asymmetric transistor while preventing formation of a halo region proximate a drain region of the asymmetric transistor. A third halo region of a second dosage greater than the first dosage is formed by implanting off-axis through the second opening.

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Edward Ehrichs, “Simplified Masking for Asymmetric Halo,” U.S. Appl. No. 10/883,925, filed Jul. 2, 2004.
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Terence B. Hook et al.;High-Performance Logic and High-Gain Analog CMOS Transistors Formed by a Shadow-Mask Technique With a Single Implant Step;IEEE Transactions on Electron Devices, vol. 49, No. 9, Sep. 2002; pp. 1623-1627.

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