Approach to integrate salicide gate for embedded DRAM devices
Approach to prevent spacer undercut by low temperature...
Approach to prevent undercut of oxide layer below gate...
Aqueous ammonium hydroxide amorphous silicon etch method for...
Architecture to monitor isolation integrity between floating...
Area-efficient electrically erasable programmable memory cell
Area-efficient stack capacitor
Arrangement and method for DRAM cell using shallow trench isolat
Array architecture and process flow of nonvolatile memory...
Array of nanoscopic mosfet transistors and fabrication methods
Array of nanoscopic MOSFET transistors and fabrication methods
Assembly process
Asymmetric channel transistor and method for making same
Asymmetric epitaxy and application thereof
Asymmetric field effect transistor structure and method
Asymmetric gates for high density DRAM
Asymmetric halo implants
Asymmetric hetero-doped high-voltage MOSFET (AH 2 MOS)
Asymmetric MOS technology power device
Asymmetric segmented channel transistors