Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-19
2001-07-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000
Reexamination Certificate
active
06258668
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to semiconductor memories and in particular flash electrically erasable and programmable read only memories (EEPROM) for use in mass storage applications.
2. Description of Related Art
A major driving force behind semiconductor flash memory devices has been the cost per bit reduction achieved by reduction of cell sizes by utilizing process scaling techniques. An attempt to accelerate the rate cost reduction has fostered several ongoing activities to develop reliable multiple bits per storage cell devices and reduction in cell size using innovative cell architecture.
In the Intel Technology Journal, 4th quarter 1997, “Intel StrataFlash™ Memory Technology Overview”, (Atwood et al.), a stacked gate structure is described in which an ETOX process is used to produce a multiple level cell to store two bit in the same memory cell. In U.S. Pat. No. 5,828,600 (Kato et al.) is described a nonvolatile semiconductor memory where the cells are a MOSFET with a floating gate and have low power, high speed and reduced cell area. An additional objective of the invention is to insure the number of program and erase operations of 10
6
. In U.S. Pat. No. 5,400,279 (Momodomi et al.) discloses a nonvolatile memory device with a NAND cell structure. In U.S. Pat. No. 5,095,344 (Harari) a highly compact flash memory device is disclosed using an intelligent programming technique to allow multiple bits to be stored in each cell and an intelligent erase program to extend the useful life of each cell. In U.S. Pat. No. 5,029,130 (Yeh) a single transistor electrically programmable and erasable memory cell is disclosed using a spit gate which allows the control gate to control a portion of the channel and the floating gate to control the remaining portion of the channel.
There arc several approaches in prior art to form nonvolatile memories potentially suitable for mass storage requirements. These approaches range from storing more than one bit of information in a cell to producing highly compact devices to using different architecture that create NAND and AND arrays to minimize the die size. As history has shown there is a relationship between larger memory density, higher utilization and lower memory price, and this seems to track for flash memories as well. Much of the improvement to date has been through smaller geometry's. Flash memory's are used in a wide array of products, and the non volatility makes a flash memory a candidate for mass storage applications.
SUMMARY OF THE INVENTION
In this invention a process is disclosed for a split gate flash memory cell that is laid out in such a way as to promote a highly integrated and tightly coupled array to promote high density. An array scheme is shown to demonstrate how the split gate cells are operated to minimize array size and at the same time avoid unwanted disturb conditions using program and erase block partitions. This produces a small and compact design, and achieves a high storage density with a long operating life making the invention useful for mass storage applications.
The process used to develop the spit gate flash memory cell is based on conventional CMOS processes. A plurality of wells are formed in a semiconductor substrate and a gate oxide layer is grown on the substrate. The wells are ion implanted to adjust, Vt, the threshold voltage of the well. A layer of polysilicon is deposited on the surface of the substrate with a layer of dielectric deposited on top of the polysilicon. The combination of the dielectric and the polysilicon are etched to form a plurality of floating gate structures. Disposable spacers are formed on the sides of the floating gate structures. The floating gate structures are sufficiently thick to produce an offset to allow an adequate select (control) transistor channel length. The thickness of the dielectric in the floating gate structure also reduces the floating gate to control gate capacitive coupling.
After the floating gate structures have been formed with disposable sidewall spacers, drains and sources are ion implanted into the substrate using the floating gate structure as a mask. Photo resist is applied to the wafer and areas over the implanted sources including a portion of the floating gate structures are opened up so that the sidewall spacers adjacent to the implanted sources can be removed. After the sidewall spacers on the source side are removed, a double diffused source is ion implanted into the area of the substrate previously implanted to contain the source of the split gate transistors. The source of each transistor is ion implanted into the substrate to bring the source close to the edge of the floating gates without the removed sidewall spacer. The masking step to remove the source side sidewall spacer is also used for double diffusing the source implant and ion implanting the source up to the edge of the floating gates.
After the photoresist is removed an isolation oxide is formed over the areas of the drains and sources. The disposable sidewall spacer remaining on the floating gate structure retards the isolation oxidation at the floating gate polysilicon layer. The remaining spacer is removed and an interpoly dielectric is grown on the sides of the floating gate. A second layer of polysilicon is deposited and the control gates of the split gate flash memory cells are masked and etched in the form of word lines that extend the length of a row of a memory array.
The split gate flash memory cells are arranged on the semiconductor substrate such that bit lines and source lines run vertically between the split gate flash memory cells. The sources are shared with a first column of cells on one side of a particular column of memory cells and the drains are shared with a second column of cells on the other side of the particular column of memory cells. Each source line is connected to the sources of two columns of flash memory cells and extends the full height of the memory array. Each bit line is connected to the drains of two columns of flash memory cells and extends the full height of the memory array. The second level polysilicon used to form the control gates (also known as select gates) of the stacked gate memory cells forms the wordlines of the memory array which extends across the width of the array. Each wordlines run orthogonal to the source lines and the bit lines and connect the control gates of each split gate memory cell in a memory row together.
A split gate flash memory cell can be thought of as two transistors in series, a select transistor controlled by the control gate and the memory transistor controlled by the floating gate. During programming a voltage which is approximately equal to the threshold voltage, Vt, of the select transistor is applied to the wordline connected to the control gate of the cell being programmed. The voltage on the wordline is sufficient to turn on the channel of the select transistor. The drain is at zero volts when the cell is to be programmed and at Vdd when the cell is not to be programmed. When the cell is to be programmed, the drain is biased at zero volts, and the source is at a high positive voltage. The source to drain voltage difference generates hot electron in the channel of the memory cell to be programmed. The source is capacitive coupled to the floating gate, and the field between the floating gate and the source efficiently transports channel hot electrons onto the floating gate of the cell being programmed.
Programming cells in a memory array of this invention is done in a vertical page associated with a source line. Since two columns of memory cells are connected to the same source line, the bit line connecting to the drains of the column of cells not to be programmed is connected to Vdd. The source line connected to the cell to be programmed is at a high voltage and the wordline connected to the cell to be programmed is at Vt. All other source lines, bit lines and wordlines are biased at zero volts. Programming the next transistor in the vertical page bec
Chan Vei-Han
Chen Hung-Sheng
Lee Peter W.
Ackerman Stephen B.
Aplus Flash Technology Inc.
Lee Calvin
Saile George O.
Smith Matthew
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