Area-efficient electrically erasable programmable memory cell

Details Area-efficient electrically erasable programmable memory cell Area-efficient electrically erasable programmable memory cell

2011-04-05

2011-04-05

Tran, Long K (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S003000, C438S201000, C438S211000, C438S223000, C438S257000, C257SE21409, C257SE21437, C257SE21545, C257SE21550

Reexamination Certificate

active

07919368

ABSTRACT:
Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.

REFERENCES:
patent: 7095076 (2006-08-01), Han et al.
patent: 7144775 (2006-12-01), Chaudhry et al.
patent: 2006/0262599 (2006-11-01), Wu
patent: 2007/0200180 (2007-08-01), Irani et al.
patent: 2010/0039868 (2010-02-01), Mitchell et al.

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