Architecture to monitor isolation integrity between floating...

Details Architecture to monitor isolation integrity between floating... Architecture to monitor isolation integrity between floating...

2007-06-05

2007-06-05

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S017000, C438S257000, C257SE21680

Reexamination Certificate

active

10833179

ABSTRACT:
A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.

REFERENCES:
patent: 6037625 (2000-03-01), Matsubara et al.
patent: 6541324 (2003-04-01), Wang
patent: 6756806 (2004-06-01), Yang et al.
patent: 2004/0108539 (2004-06-01), Kim
patent: 2004/0110362 (2004-06-01), Rudeck

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