Approach to integrate salicide gate for embedded DRAM devices

Details Approach to integrate salicide gate for embedded DRAM devices Approach to integrate salicide gate for embedded DRAM devices

2001-09-27

2002-05-07

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S255000, C438S673000

Reexamination Certificate

active

06383863

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process used to form salicide layers on components of an embedded, dynamic random access memory, (DRAM), device.
(2) Description of Prior Art
The performance of DRAM cells, embedded in logic arrays, can be deleteriously influenced by the high resistance of the DRAM word lines. The desired objective of low resistance for narrow width, DRAM word lines, can be difficult to satisfy via use of polycide word lines, comprised of an overlying metal silicide layer, such as tungsten silicide, on an underlying polysilicon shape. The higher. than desired resistance of the tungsten silicide component may require metal strapping to reduce the resistance—capacitance (RC), delay, since the memory cell, in the DRAM circuit, is accessed through the word line structure. The need for metal strapping to increase performance results in additional process complexity and increased cost.
This invention will describe a process in which a self-aligned silicide (salicide), formation procedure, easily integratable with logic devices, is used to reduce the resistance of the DRAM word line structures, without the use of metal strapping. In addition this invention will teach the process for integrating a salicide formed, cobalt silicide layer on the DRAM word line, as well as on the crown shaped capacitor structure, while preventing formation of the cobalt suicide layer on the shallow DRAM source/drain regions. The use of self-aligned contact (SAC) openings for capacitor and bit line openings, in addition to the formation of insulator spacers on the sides of the structures in these openings, allow sufficient space to accommodate a salicided word line contact structure, a capacitor structure, and a bit line structure, without increasing the DRAM cell size. Prior art, such as Sun et al, in U.S. Pat. No. 5,930,618, describe a process for integrating logic and DRAM memory, however that prior art uses; the higher resistance polycide gate for the DRAM device, while the lower resistance salicide gates are used only for logic devices.
SUMMARY OF THE INVENTION
It is an object of this invention to reduce the resistance of the word line structures in embedded DRAM devices, via the use of salicide procedures.
It is another object of this invention to minimize DRAM cell size via a self-aligned procedure used to form salicide layers on the DRAM word line structures, while not forming salicide layers on the DRAM source/drain regions.
It is still another object of this invention to form cobalt silicide on the top surfaces of capacitor and bit line structures, of a capacitor under bit line design, while simultaneously forming cobalt silicide layers on the DRAM word line structures.
In accordance with the present invention a process for self-aligning the formation of a salicide layer on embedded DRAM, word lines, capacitor, and bit line structures, while preventing salicide formation on the embedded DRAM source/drain region, is described. After formation of source/drain regions, in regions of semiconductor substrate not covered by silicon nitride capped, polysilicon gate structures, a planarized composite insulator layer is formed. Capacitor and bit line openings are formed in the planarized, first composite insulator layer, with the bottom portion of these openings self-aligned to the silicon nitride capped, polysilicon gate structures. The capacitor and bit line openings are then lined with storage node structures and an capacitor dielectric layer, then filled with a top plate component. A selective etch is then employed to anisotropically remove the planarized, first composite insulator layer, as well to remove the capping insulator components of the silicon nitride capped, polysilicon gate structures, exposing the top surfaces of the polysilicon gate structures. The same selective etch procedure simultaneously defines an insulator spacer on the sides of the capacitor and bit line structures, resulting in self-alignment between the capacitor and bit line structures, lined with the insulator spacers, and the adjacent, uncapped, polysilicon gate structures. The source/drain regions remain unexposed, underlying the capacitor and bit line structures. A salicide formation procedure is next used to form a cobalt silicide layer on the exposed top surface of the uncapped, polysilicon gate structures, as well as on the top surface of the capacitor and bit line structures, with the insulator spacers located on the sides of the capacitor and bit line structures preventing shorting between these salicided components. After formation of a planarized, second composite insulator layer, openings are formed in this composite insulator layer exposing top portions of a salicided word line structure, and a top portions of the salicided bit line structure. Conductive plug and metal structures are then formed in these openings, contacting the word line structure, as well as the bit line structure, of the capacitor under bit line, embedded DRAM cell.


REFERENCES:
patent: 5858831 (1999-01-01), Sung
patent: 5879986 (1999-03-01), Sung
patent: 5930618 (1999-07-01), Sun et al.
patent: 6074915 (2000-06-01), Chen et al.
patent: 6096595 (2000-08-01), Huang
patent: 6150214 (2000-11-01), Kaeriyama
patent: 6291335 (2001-09-01), Schnabel et al.

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