Approach to prevent spacer undercut by low temperature...

Details Approach to prevent spacer undercut by low temperature... Approach to prevent spacer undercut by low temperature...

2002-02-07

2003-08-26

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S366000, C438S775000, C438S791000, C438S184000, C438S595000, C257S384000

Reexamination Certificate

active

06610571

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to prevent gate spacer undercut in the creation of gate electrode structures.
(2) Description of the Prior Art
The art of creating Complementary Metal Oxide Silicon (CMOS) devices is well known in semiconductor technology.
FIG. 1
shows a cross section of a conventional CMOS device, the creation of this device will be briefly highlighted using the device elements that are highlighted in FIG.
1
. The process of creating a CMOS device starts by
providing a semiconductor substrate
10
. Insulation regions
12
, that bound the active region in the surface of substrate
10
, isolate the active region in the surface of substrate
10
and may be created using Oxide (FOX) isolation or Shallow Trench Isolation (STI). A thin layer
16
of gate oxide is grown over the surface of the substrate
10
in the active device region. To create the gate structure, a layer
14
of polysilicon is grown over the thin layer
16
of gate oxide. The polysilicon layer
14
is masked and the exposed polysilicon and the thin layer of oxide are etched to create the polysilicon gate
14
that is separated from the substrate
10
by the remaining thin layer
16
of oxide. The doping of the source/drain regions starts with creating the lightly N
+
doped diffusion (LDD) regions
32
/
34
. The sidewall spacers
22
for the gate structure are formed after which the source (
18
) and drain (
20
) regions doping is completed by doping these source/drain regions
18
/
20
to the desired level of conductivity using an impurity implantation.
Low resistivity contact points
24
(to the source
18
),
26
(to the drain
20
) and
28
(to the electrode gate
14
) are then formed by first depositing a layer of titanium or cobalt with TiN over the surface of the source/drain regions and the top surface of the gate electrode. This titanium or cobalt is annealed causing the deposited titanium or cobalt to react with the underlying silicon of the source/gain regions and the doped surface of the gate electrode. This anneal forms layers of titanium silicide or cobalt silicide
24
/
26
on the surfaces of the source/drain regions and layer
28
on the top surface of the gate electrode. Cobalt with TiN are used to form cobalt salicide in which the TiN serves as a barrier layer.
Metal contacts with the source (
40
) and drain (
42
) regions and the gate electrode (
44
) are formed as a final step. A layer
30
of dielectric, such as silicon oxide, is blanket deposited over the surface of the created structure. This layer of dielectric is patterned and etched to create contact openings
36
/
37
over the source/drain regions and opening
38
over the top surface of the gate electrode. A metallization layer is deposited over the patterned layer
30
of dielectric, establishing the electrical contacts
40
/
42
with the source/drain regions and
44
with the top surface of the gate electrode.
The conventional methods that are employed to create CMOS devices address such concerns as the thickness and uniformity of the layer of gate oxide, a shallow junction depths required for the device impurity implantations, the impurity content of the layer of gate dielectric, the dielectric constant of the materials for the gate dielectric, prevention of the migration of impurity implantations (such as boron, implanted into a layer of polysilicon to create the conductivity of the body of the gate electrode) into the channel region of the underlying substrate, causing leakage current of the gate electrode to the substrate, device switching speed and the like.
The invention addresses concerns of damage that is caused to the layer of gate spacer oxide. The layer of gate spacer oxide (also referred to as liner oxide) underlies the gate spacers and is interposed between the body of the gate electrode and the gate spacers, overlying the sidewalks of the body of the gate electrode. An overetch of the layer of gate spacer oxide causes the gate spacer oxide to be partially removed from below the gate spacer, creating an undercut below the gate spacer. Methods are provided by the invention to prevent this undercut.
U.S. Pat. No. 6,200,868 B1 (Mase et al.) shows a nitridation process to prevent gate spacer undercut.
U.S. Pat. No. 6,187,676 (Kim et al.) shows a nitridation process to cover an undercut.
U.S. Pat. No. 6,144,071 (Gardner) shows a related method.
SUMMARY OF THE INVENTION
It is the primary objective of the invention to reduce undercut in the layer of gate spacer oxide of a gate electrode.
Another objective of the invention is to improve isolation of the gate electrode.
Yet another objective of the invention is to prevent the accumulation of semiconductor materials or foreign particles in openings created under the gate spacers of a gate electrode.
In accordance with the objectives of the invention a new method is provided for the removal of liner oxide from the surface of a gate electrode during the creation of the gate electrode. A layer of gate oxide is formed over the surface of a substrate, a layer of gate electrode such as polyimide is deposited over the layer of gate oxide. The gate electrode and the layer of gate oxide are patterned. A layer of liner oxide is deposited, gate spacers are formed over the liner oxide, exposing surfaces of the liner oxide. The created structure is nitrided by a plasma stream containing N
2
/H
2
, reducing the etch rate of the exposed liner oxide. The liner oxide is then removed by applying a wet etch, contact regions to the gate electrode are salicided.


REFERENCES:
patent: 5358879 (1994-10-01), Brady et al.
patent: 5648284 (1997-07-01), Kusunoki et al.
patent: 5847428 (1998-12-01), Fulford, Jr. et al.
patent: 5895955 (1999-04-01), Gardner et al.
patent: 5939333 (1999-08-01), Hurley et al.
patent: 6144071 (2000-11-01), Gardner et al.
patent: 6187676 (2001-02-01), Kim et al.
patent: 6200868 (2001-03-01), Mase et al.
patent: 6350708 (2002-02-01), Hurley
patent: 6503846 (2003-01-01), Niimi et al.

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