Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-04-29
2000-07-11
Monin, Jr., Donald L.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438243, 438246, 438388, 438424, 257296, 257305, H01L 2170
Patent
active
060872144
ABSTRACT:
A semiconductor structure uses a shallow trench isolation (STI) region to realize a capacitor trench of a reduced size. Consistent with one embodiment of fabricating a memory cell, the invention includes selectively removing portions of a substrate using a patterned mask to form a capacitor trench and an isolation trench at least partially around the capacitor trench. An oxide is formed in the isolation trench and the capacitor trench and the oxide so selectively removed in the capacitor trench. Portions of the substrate defining the base and sidewalls of the capacitor trench are then doped and a capacitor dielectric is formed in the capacitor trench, leaving a portion of the trench unfilled. A polysilicon layer is formed it the unfilled portion of the capacitor trench and over the capacitor dielectric to form a plate of the storage capacitor.
REFERENCES:
patent: 4617071 (1986-10-01), Vora
patent: 4637836 (1987-01-01), Flatley et al.
patent: 4645564 (1987-02-01), Morie et al
patent: 4731342 (1988-03-01), Ishiuchi
patent: 4830981 (1989-05-01), Baglee et al.
patent: 4833099 (1989-05-01), Woo
patent: 4842675 (1989-06-01), Chapman et al.
patent: 5027185 (1991-06-01), Liauh
patent: 5185284 (1993-02-01), Motonami
patent: 5364803 (1994-11-01), Lur et al.
patent: 5545925 (1996-08-01), Hanaoka
patent: 5793075 (1998-08-01), Alsmeier et al.
patent: 5811347 (1998-09-01), Gardner et al.
C.T. Liu et al. "High Performance 0.2.mu.m CMOS with 25 .ANG. Gate Oxide Grown on Nitrogen Implanted Si Substrates", IEDM 96-499, 1996.
Hidetoshi Koike et al., "Dual-Polycide Gate Technology Using Regrowth Amorphous-Si to Suppress Lateral Dopant Diffusion", IEEE Transactions on Electron Devices, vol. 44, No. 9, Sep. 1997.
Charles L. Chu et al., "Technology Limitations fir N+/P+ Polycide Gate CMOS due to Lateral Dopant Diffusion in Silicide/Polysilicon Layers", IEEE Electron Device Letters, vol. 12, No. 12, Dec. 1991.
I. Suni et al., "Thermal Oxidation of Reactively Sputtered Titanium Nitride and Hafnium Nitride Films", J. Electrochem Soc.: Solid-State Science and Technology, May 1993.
B. El-Kareh et al. "The evolution of DRAM cell technology", Solid State Technology, May, 1997.
Billy L. Crowder et al. 1 .mu.m MOSFELT VLSI Technology: Part VII-Metal Silicide Interconnection Technology-A Future Perspective, IEEE Transactions on Electron Devices, vol. ED-26, No 4, Apr. 1979.
T. Paul Chow et al. Refractory Metal Silicides: Thin Film Properties and Processing Technology, IEEE Transactions on Electron Devices, vol. ED-30, No. 11, Nov. 1983.
K. Fujii et al. A Thermally Stable Ti-W Salicide for Deep-Submicron Logic with Embedded DRAM, IEDM 96-451.
Marc Wittmer "Properties and microelectric applications of thin films of refractory metal nitrides", J. Vac. Sci. Technol. A 3 (4), Jul/Aug. 1985.
Effiong Ibok et al. "A characterization of the Effect of Deposition Temperature on Polysilicon Properties", J. Electrochem. Soc., vol. 140, No. 10, Oct. 1993.
S. Shimizu et al. "Impact of Surface Proximity Gettering and Nitrided Oxide Side-Wall Spacer by Nitrogen Implantation on Sub-Quarter Micron CMOS LDD FETs", IEDM 95-859.
M.T. Takagi et al. "A Novel 0.15 .mu.m CMOS Technology using W/WNx/Polysilicon Gate Electrode and Ti Silicided Source/Drain Diffusions", IEDM 96-455.
Jerome B. Lasky et al. "Comparison of Transformation to Low-Resistivity Phase and Agglomeration of TiSi2 and CoSi2", IEEE Transactions of Electron Devices, vol. 38, No. 2 Feb. 1991.
Bijan Davari et al. "A High-Performance 0.25-.mu.m CMOS Technology: II-Technology", IEEE Transactions on Electron Devices, vol. 39, No. 4 Apr. 1992.
G.E. Georgiou et al. "Thermal Stability Limits of Thin TiSi2", J. Electrochem. Soc., vol. 141, No. 5, May 1994.
Tomohisa Mizuno et al. "Si3N4/SiO2 Spacer Induced High Reliability in LDDMOSFET and Its Simple Degradation Model", IEDM 88.
D. Pramanik et al. "Formation of Titanium Silicide by Rapid Thermal Annealing", Semiconductor International, May, 1985.
M.Y. Tsai et al. "One-Micron Polycide (Wsi2 on Poly-Si) MOSFET Technology", J. Electrochem. Soc.: Solid-State Science and Technology, Oct. 1981.
B. Davari et al. "A High-Performance 0.25 .mu.m CMOS Technology", IEDM 88.
A.K. Sinha et al. "Generic Reliability of the High-Conductivity TaSi2
+ Poly-Si Gate MOS Structure", IEEE 1980.
Stefan Nygren et al. "Dual-Type CMOS Gate Electrodes by Dopant Diffusion from Silicide", IEEE Transactions on Electron Devices, vol. 36, No. 6, Jun. 1989.
A. Nishiyama et al. "A Thermally Stable Salicide Process Using N2 Implantation into TiSi2", IEEE VMIC Conference, Jun. 12-13, 1990.
Keith A. Jenkins et al. "Identification of Gate Electrode Discontinuities in Submicron CMOS Technologies, and Effect on Circuit Performance", IEEE Transactions on Electron Devices, vol. 43, No. 5, May, 1996.
L.C. Parrillo et al. "A Fine-Line CMOS Technology That Uses P+ Polysilicon/Silicide Gates For NMOS and PMOS Devices", IEDM 84.
Monin, Jr. Donald L.
Pham Hoai
VLSI Technology Inc.
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