Control trimming of hard mask for sub-100 nanometer...
Controlled linewidth reduction during gate pattern formation usi
Conversion of amorphous layer produced during IMP Ti deposition
Cross-contamination control for processing of circuits...
Cross-contamination control for semiconductor process flows...
CVD-based process for manufacturing stable low-resistivity...
CVD-PVD deposition process
Damage free gate dielectric process during gate electrode plasma
Damascene process for MOSFET fabrication
Damascene T-gate using a spacer flow
Dark field image reversal for gate or line patterning
Dense flash EEPROM cell array and peripheral supporting circuits
Device performance improvement by heavily doped pre-gate and...
Device structure and method for reducing silicide encroachment
Differential poly-edge oxidation for stable SRAM cells
Dishing-free gap-filling with multiple CMPs
Dopant diffusion-retarding barrier region formed within...
Dopant implantation processing for improved source/drain...
Double gate oxide layer method of manufacture
Double spacer technology for making self-aligned contacts (SAC)