Controlled linewidth reduction during gate pattern formation usi

Details Controlled linewidth reduction during gate pattern formation usi Controlled linewidth reduction during gate pattern formation usi

1997-08-01

2000-08-22

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438636, 438671, 438738, 438951, 438952, H01L 213205, H01L 214763, H01L 2144, H01L 21302

Patent

active

061071722

ABSTRACT:
A gate is formed by creating a wafer stack, that includes a gate conductive layer over a substrate layer, depositing a SiO.sub.x N.sub.y layer over the conductive layer to act as a bottom anti-reflective coating (BARC), and forming a resist mask on the SiO.sub.x N.sub.y layer. Next, the resist mask is isotropically etched to further reduce the critical dimensions of the gate pattern formed therein, and then the underlying BARC and wafer stack are etched to form a gate out of the conductive layer.

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