CVD-PVD deposition process

Details CVD-PVD deposition process CVD-PVD deposition process

2002-06-11

2004-04-06

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S675000

Reexamination Certificate

active

06716733

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
Embodiments of the present invention generally relate to semiconductor processing and integrated circuits. More particularly, the invention relates to the deposition of metal in apertures to form uniform, void-free interconnections between conducting layers in high aspect ratio applications.
2. Description of the Related Art
Sub-quarter micron multilevel metallization is one of the key technologies for the next generation of very large scale integration (VLSI). The multilevel interconnects that lie at the heart of this technology require planarization of high aspect ratio apertures, including contacts, vias, lines or other features having aperture widths less than 0.25 &mgr;m and aperture depths greater than the aperture widths. Reliable formation of these interconnects is very important to the success of VLSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Metal interconnects are typically formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition and/or sequential combinations thereof. Generally, PVD metal films provide superior reflectivity because of better crystalline growth and orientation of the deposited atoms. However, because PVD generally requires directional sputtering from a target in a given direction, it is difficult to achieve conformal layers on semiconductor features, i.e., a layer of uniform thickness on the sides and base of the features. On the other hand, CVD metal films provide excellent conformal coverage of features but less superior crystalline orientation and thus lower reflectivity. Highly oriented crystalline growth of conducting layers is desirable because of the contribution of crystalline growth and orientation to electromigration resistance. Electromigration is a diffusive process in which the atoms of a solid move from one place to another under the influence of electrical forces. Electromigration can result in voids and thus limits the maximum current that can be carried by a conductor without its rapid destruction.
Aluminum (Al) layers formed by chemical vapor deposition, like other CVD processes, provide good conformal aluminum layers for very small geometries, including sub-quarter micron (<0.25 &mgr;m) apertures, at low temperatures. Therefore, CVD of aluminum is a common method used to fill small apertures. However, recent transmission electron microscopy data (TEM) has revealed that voids exist in many of the apertures deposited with CVD Al even though electric tests of these same apertures do not evidence the existence of a void. Furthermore, aluminum deposited by currently used CVD processes typically exhibits a rough surface morphology, poor crystalline growth, and low reflectivity.
TEM studies of various CVD Al layers formed on substrates indicate that the formation of voids occurs through a key hole process wherein the top portion of the via becomes sealed before the via has been entirely filled. Although a thin conformal layer of CVD Al can typically be deposited in high aspect ratio contacts and vias at low temperatures to line the walls and the bottom of the features, continued CVD deposition to completely fill the contacts or vias typically results in the formation of voids therein. Extensive efforts have been focused on elimination of voids in metal layers by modifying CVD processing conditions. However, the results have not yielded a satisfactory method of manufacturing void free structures.
An alternative technique for metallization of high aspect ratio apertures is hot planarization of aluminum through physical vapor deposition (PVD). The first step in this process requires deposition of a thin layer of a refractory metal such as titanium (Ti) on a patterned wafer to form a wetting layer which facilitates flow of the Al during the PVD process. Following deposition of the wetting layer, the next step requires deposition of either (1) a hot PVD Al layer, or (2) a cold PVD Al layer followed by a hot PVD Al layer onto the wetting layer. However, hot PVD Al processes are very sensitive to the quality of the wetting layer, substrate condition, and other processing parameters. Small variations in processing conditions and/or poor coverage of the wetting layer can result in incomplete filling of the contacts or vias, thus creating voids. Hot PVD Al processes may be performed at temperatures above about 450° C. Because the PVD wetting process provides poor coverage of high aspect ratio, sub-micron via sidewalls, hot PVD Al does not provide reliable filling of the contacts or vias. Even at higher temperatures, PVD processes may result in a bridging effect whereby the opening of the contact or via is closed because the deposition layer formed on the top surface of the substrate and the upper walls of the contact or via join before the floor of the contact or via has been completely filled.
One attempt at filling high aspect ratio sub-quarter micron contacts and vias, disclosed in U.S. Pat. No. 5,877,087, incorporated by reference herein, uses a thin bonding layer deposited first over the surface of the contacts or vias, followed by a CVD layer, and then a PVD layer. The thin bonding layer is preferably a metal having a relatively higher melting point temperature than the subsequent CVD and PVD metals. However, the problem of the via or contact opening being bridged by the CVD and PVD processes still remains, and voids may still form in the contacts or vias. Furthermore, the crystalline structure of the aluminum deposited by the methods described in U.S. Pat. No. 5,877,087 may not be optimal.
Another attempt at filling high aspect ratio sub-quarter micron contacts and vias is disclosed in U.S. patent application Ser. No. 09/127,010. U.S. patent application Ser. No. 09/127,010 describes depositing a metal layer in an aperture formed on a substrate by CVD, annealing the substrate at a low pressure to eliminate any voids in the metal, and depositing another metal layer by PVD. While this process may reduce the number of voids in a structure, a method of depositing aluminum with improved surface morphology and/or crystalline growth is still desired. Therefore, there is a need for a process for depositing metals that results in the formation of a substrate with a smoother and/or improved surface morphology.
SUMMARY OF THE INVENTION
The present invention generally provides a method for depositing metal in an aperture formed on a substrate. More particularly, the present invention provides a method for filling apertures, such as high aspect ratio, sub-quarter micron contacts and vias.
One aspect of the invention provides a method for forming a feature on a substrate by chemical vapor depositing a first metal on the substrate to provide conformal coverage of the aperture surfaces. A second metal is physical vapor deposited over the first metal at a low temperature, i.e., a substrate temperature between about 25° C. and about 300° C. The physical vapor deposition is performed without any backside gas or chucking. The substrate is then heated to a temperature, such as between about 400° C. and about 550° C. Heating the substrate allows the deposited metal to reflow and substantially fill the aperture with few if any voids. The metal deposition and heating steps contribute to a smooth surface morphology of the substrate.
Another aspect of the invention further provides depositing a wetting layer on the substrate before chemical vapor depositing a first metal on the substrate. After the substrate is treated with the physical vapor desposition and heating steps provided in the first aspect of the invention, another metal is physical vapor deposited, preferably using a high power and a high temperature, on the substrate. Optionally, the substrate is then heated to allow the deposited metals to reflow and to further enhance the surface morphology of the substrate.
In another aspect of the invention, the processes described herein are performed in an integrated processing system that includes both

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