Damascene process for MOSFET fabrication

Details Damascene process for MOSFET fabrication Damascene process for MOSFET fabrication

1999-04-05

2002-03-05

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S199000, C438S259000, C438S585000, C438S633000, C438S639000

Reexamination Certificate

active

06352913

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to the fabrication of Metal Oxide Semiconductor Field Effect Transistors (MOSFET) integrated circuits (ICs), and more particularly to the fabrication of ICs having very thin gate dielectric layers with high dielectric constant and with metal gate electrodes.
As is known in the art, complex high speed IC circuits require very thin gate dielectric layers, and as close to zero gate electrode resistance as practical in order to provide fast low cost circuit operation. As is also well known in the art, there exists a problem with unwanted depletion of even heavily doped polysilicon gate electrodes which results in an effective increase in the thickness of thin gate oxide layers. This problem results in poor control over transistor turn-off voltage levels at short channel lengths, i.e., what is known as the short channel effect. For transistors with relatively thick gate oxides, this poly depletion effect is not significant, but with MOS gate oxides approaching 2.5 nm, the effect unacceptably reduces transistor performance.
It is well known that the use of a metal as the gate electrode eliminates the poly depletion problem and the resulting undesirable changes in the threshold voltage. It is also known that the use of polysilicon has an advantage over the use of metal for gate electrodes due to the ability to differently dope the polysilicon for different work functions in the two parts of a CMOS gate. Thus two different metals (i.e., with two different work functions) could be required for efficient CMOS devices. Two different metal gates raises the possibility that the two different types of transistors would have a systematic and unpredictable variation in what is known as the gate length, and hence unpredictable transistor performance.
Another problem in the art is that as the gate oxide becomes thinner to improve transistor performance, the thinner gate can not prevent gate electrode current from tunneling into the channel region. It would solve a known problem in the art to provide a gate dielectric that has a very low effective electrical capacitive thickness for high transistor performance, but also has low tunneling current. Many such “high k” materials are under investigation, such as Silicon Nitride (Si3N4), Barium Strontium Titanate (BST), Titanium Dioxide (TiO2), and Tantalum Pentoxide (Ta2O5), but problems exist in processing polygate IC devices with these dielectrics because of what are known as etch selectivity issues during the wet chemical, plasma, and reactive ion etches commonly used in the art.
Another problem in the art is to minimize the parasitic transistor capacitance, which slows the transistor down. A known method to reduce parasitic junction capacitance is to restrict the channel dopant region to minimize the overlap to the source/drain (S/D) region by use of a masked implant. This process is restricted by the alignment tolerances, and a self aligned process would solve this problem.
Thus a problem exists in the art of polysilicon gate material depleting under the influence of the gate voltage and effectively increasing the gate oxide thickness and decreasing the transistor performance. There also exists a problem with gate electrode to channel tunneling leakage with thin gate oxide thickness and the associated etch selectivity problems. Finally, there exists a problem of minimizing transistor parasitic capacitance.
SUMMARY OF THE INVENTION
In accordance with the invention, an improved thin gate oxide transistor is made by depositing and patterning first and second dielectric layers on a semiconductor substrate to define and open gate regions, depositing or growing a silicon dioxide or high dielectric constant gate dielectric layer and depositing a gate polysilicon or metal layer. Removing the polysilicon/metal and gate dielectric layer in non gate regions by use of chemical-mechanical polishing (CMP), and stripping the remaining parts of the first and second dielectric layers. Ion implanting a S/D extension region, depositing and patterning a spacer dielectric, and ion implanting source and drain regions completes the transistor. With such a procedure, the etch selectivity problems are resolved, the poly depletion is greatly reduced and the gate dielectric layer may be made thicker, with reduced tunneling and parasitic capacitance.
In another embodiment a CMOS device is provided using a masking layer after the defining of the gate regions to protect P channel regions while forming N channel gates, and a second masking layer to protect the N channel regions while the P channel gates are formed.
In yet another embodiment, a CMOS device is provided using a self aligned threshold voltage implant into the open gate regions defined by patterning the first and second dielectric layers, thereby reducing transistor parasitic capacitances and improving performance.


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