Conversion of amorphous layer produced during IMP Ti deposition

Details Conversion of amorphous layer produced during IMP Ti deposition Conversion of amorphous layer produced during IMP Ti deposition

2000-06-23

2002-05-14

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S653000, C438S654000, C438S655000, C438S656000, C438S660000, C438S682000

Reexamination Certificate

active

06387790

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor manufacturing, and more particularly to a method of converting an amorphous region produced during the annealing of an ionized metal plasma (IMP) Ti/TiN liner into a substantially crystalline region. The substantially crystalline region and the Ti/TiN liner are used for lining a metallic silicide, such as CoSi
2
. The present invention is also directed to an inventive crystalline-containing liner and a contact structure which includes the same.
BACKGROUND OF THE INVENTION
In the field of complementary metal oxide semiconductor (CMOS) devices, the aspect ratio of metal contacts is increasing rapidly. Robust liner processes are thus required to assure a manufacturable process. Specifically, liner materials that provide uniform and continuous coverage of high aspect ratio contact holes are required. The term “high aspect ratio” is used herein to denote a contact hole whose height (H) to width (W) ratio, H/W, is greater than 2.
One liner material that is known to provide good coverage of high aspect ratio contact holes is ionized metal plasma (IMP) deposited titanium, Ti. However, upon furnace annealing the IMP deposited Ti, an amorphous region forms between the deposited Ti liner and the metal silicide contact. The term “amorphous” is used herein to denote a region that lacks organization and unity.
When CoSi
2
is employed as the contact material, the amorphous region consists of Co, Si and Ti. It is known, in this regard, that Co-containing TiSi
x
(a titanium silicide) is usually amorphous because of the mismatch between Co and Ti atoms and that this amorphous region cannot be converted to crystalline TiSi
x
and CoSi
x
until a temperature of between 650° C.-700° C. is reached.
An amorphous region comprising TiSi
x
is undesirable in contact structures because the amorphous region is much more reactive than a fully converted silicide. Moreover, the TiSi
x
phase of titanium silicide has a much lower resistance than crystalline TiSi
2
. The amorphous region of IMP deposited Ti is undesirable since it leaves the annealed liner marginal, i.e., the presence of a liner containing an amorphous region of IMP Ti typically results in liner failure.
There is thus a continued need in the semiconductor industry to develop new and improved methods that can solve the amorphous (Ti,Co)Si problem mentioned above.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a substantially crystalline-containing liner that provides good coverage (i.e., uniformity and continuity) of a high aspect ratio, H/W is greater than 2, contact hole.
Another object of the present invention is to provide a method of fabricating a substantially crystalline-containing liner that has a good contact resistance associated therewith.
A still further object of the present invention is to provide a method of converting an amorphous region formed during the annealing of ionized metal plasma deposited Ti into a substantially crystalline region. The term “substantially crystalline” is used herein to denote a region that has high-organization and unity.
An even further object of the present invention is to provide a substantially crystalline-containing liner that is more reliable against fluoride attack in a later WF
6
deposition processing step.
A yet further object of the present invention is to provide a Ti/TiN liner that is not prone to cause liner failure.
These and other objects and advantages are achieved in the present invention by utilizing a ‘rapid thermal liner anneal’ (RTLA) process in which higher temperatures and shorter anneal times are employed in converting the amorphous IMP Ti region into a substantially crystalline region.
In prior art processes, annealing is typically conducted in a furnace at temperatures less than 600° C. using a forming gas such as N
2
/H
2
. In this application, the IMP deposited Ti liner material is annealed at temperatures greater than 600° C. for shorter durations than a typical furnace anneal. This RTLA step converts the amorphous region of IMP deposited Ti into a substantially crystalline region.
Specifically, in one embodiment of the present invention, the method of the present invention comprises the steps of:
(a) providing a structure having at least one contact hole formed therein, said at least one contact hole exposing at least a portion of a cobalt disilicide contact formed in a semiconductor substrate;
(b) depositing a Ti/TiN liner in said at least one contact hole by ionized metal plasma deposition; and
(c) annealing said Ti/TiN liner under conditions effective to recrystallize any amorphous region formed during said annealing into a crystalline region, said crystalline region including a TiSi
2
top layer and a CoSi
x
bottom layer.
The present invention also may include the step of: (d) forming a conductive material on said Ti/TiN liner.
In another embodiment wherein the cobalt disilicide is in contact with a polysilicon gate, the method of the present invention comprises the steps of:
(a) forming a cobalt disilicide layer on a substrate e.g., polysilicon;
(b) forming a Ti/TiN liner on said cobalt disilicide; and
(c) annealing said Ti/TiN liner under conditions effective to recrystallize any amorphous region formed during said annealing into a crystalline region.
Another aspect of the present invention relates to a semiconductor contact structure that is formed utilizing the inventive RLTA processing step of the present invention. Specifically, the contact structure of the present invention comprises:
a semiconductor substrate having a cobalt disilicide contact formed therein;
a patterned pad nitride layer on said substrate, said patterned pad nitride layer not covering said cobalt disilicide contact;
a patterned dielectric layer on said patterned pad nitride layer;
a contact hole formed in said patterned pad nitride and dielectric layers exposing said cobalt disilicide contact;
a Ti/TiN liner formed in said contact hole; and
a conductive material formed on said Ti/TiN liner in said contact hole, wherein crystallized regions of CoSi
x
and TiSi
2
are between said Ti/TiN liner and said cobalt disilicide contact.
A further aspect of the present invention relates to a liner material which comprises Ti/TiN and underlying crystalline layers of TiSi
2
and CoSi
x
.


REFERENCES:
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patent: 5643823 (1997-07-01), Ho et al.
patent: 5747866 (1998-05-01), Ho et al.
patent: 5754390 (1998-05-01), Sandhu et al.
patent: 5869389 (1999-02-01), Ping et al.
patent: 5888888 (1999-03-01), Talwar et al.
patent: 5950078 (1999-09-01), Mackawa et al.
patent: 6303490 (2001-10-01), Jeng

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