CVD-based process for manufacturing stable low-resistivity...

Details CVD-based process for manufacturing stable low-resistivity... CVD-based process for manufacturing stable low-resistivity...

1998-10-07

2001-02-13

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S652000, C438S655000, C438S656000

Reexamination Certificate

active

06187656

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of semiconductor processing and more specifically to forming poly-metal gate electrode transistors.
BACKGROUND OF THE INVENTION
In sub-quarter-micron ultra-large scale integrated circuits (ULSIs), a low-resistivity gate electrode is required to reduce limitations on the speed of MOS devices due to the gate RC delay time. Tungsten (W)-poly (Si) gate structures have lower sheet resistance than conventional poly or polycide gates. Because W reacts with Si at temperatures as low as 600° C., it is critical to have a high quality diffusion barrier between W and Si. WN and TiN are candidates as the diffusion barriers between W and poly-Si to avoid silicidation of the W film. In conventional post-gate-etch, dry/wet oxidation is used to remove the etch damage and to improve the gate dielectric strength. The gate materials including the metal materials (W and the barrier) are subjected to the oxidation. However, under selective oxidation conditions, such as the so-called wet hydrogen oxidation (WHO) procedures (Seichi Iwata et al., IEEE Transactions on Electron Devices, Vol. ED-31, No. 9, pp. 1174-1179, Sept. 1984), W-based materials will not be oxidized while TiN barrier is still subject to oxidation. Oxidation of the barrier TiN layer can result in lift-off of the W layer. Therefore, from a low-resistivity and process integration point of view, the W-poly gate electrode without TiN is preferred.
In one prior art process (Yasushi Akasaka et al., IEEE Transactions on Electron Devices, Vol. 43, No. 11, pp. 1864-1869, Nov. 1996), a PVD process is used to fabricate a W/WN/poly-Si gate electrode. WNx films were deposited on poly-Si by reactive sputtering a W target in a gas mixture consisting of Ar:N
2
=1:1. W films were continuously deposited by DC magnetron. However, the application of this process to MOS devices with a serious topography is limited. due to the poor step coverage of PVD films. In addition, excess nitrogen in the WNx layer needs to escape from the stack during thermal treatment. Because the thermal treatment occurs after the deposition of the W film, the escaping nitrogen from the WNx layer can cause delamination.
Accordingly, there is a need for a method of forming a barrier layer between the poly and metal of a gate electrode that overcomes the above problems.
SUMMARY OF THE INVENTION
The invention is a process for forming a metal-poly stack comprising the steps of: (1) deposition of silicon (with dopants) on a thin dielectric layer covered substrate, (2) deposition of metal-Nx by a CVD-based process, (3) thermal treatment to convert metal-Nx into a thermally stable barrier and to remove excess nitrogen and (4) deposition of metal.
An advantage of the invention is providing a process for forming a metal-poly structure that uses CVD films having better step coverage than the PVD films of the prior art.
Another advantage of the invention is providing a structure that is more stable in subsequent thermal processing due to the removal of excess nitrogen before the metal deposition.
Another advantage of the invention is providing a process for forming a structure that is compatible with selective oxidation for removing etching damage to a gate oxide.


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Article from IEEE Transaction on Electron Devices, vol. ED-31, No. 9, Sep. 1984, “A New Tungsten Gate Process for VLSI Applications,” pp. 1174-1179 (Seichi Iwata, Naoki Yamamoto, Nobuyoshi Kobayashi, Tomoyuki Terada and Tatsumi Mizutani).
Article from IEEE Transactions on Electron Devices, vol. 43, No. 11, Nov. 1996, “Low-Resistivity Poly-Metal Gate Electrode Durable for High-Temperature Processing,” pp. 1864-1869 (Yasushi Akasaka, Shintaro Suehiro, Kazuaki Nakajima, Tetsuro Nakasugi, Kiyotaka Miyano, Kunihiro Kasai, Hisato Oyamatsu, Member IEEE, Masaaki Kinugawa, Member IEEE, Mariko Takayanagi Takagi, Kenichi Agawa, Fumitomo Matsuoka, Member IEEE, Masakazu Kakumu, Member IEEE, and Kyoichi Suguro).

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