Cross-contamination control for processing of circuits...

Details Cross-contamination control for processing of circuits... Cross-contamination control for processing of circuits...

2011-06-28

2011-06-28

Pham, Thanhha (Department: 2894)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S261000, C438S691000, C438S745000

Reexamination Certificate

active

07968443

ABSTRACT:
A cross method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface, wherein the bevel semiconductor surface and backside semiconductor surface include silicon or germanium. A metal including high-k gate dielectric layer is formed on at least the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and backside semiconductor surface. The high-k dielectric material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed while protecting the high-k dielectric layer on the topside semiconductor surface. The selective removing includes a first oxidizing treatment, and a fluoride including wet etch follows the first oxidizing treatment. The fabrication of the IC is completed including forming at least one metal gate layer on the high-k gate dielectric layer after the selectively removing step.

REFERENCES:
patent: 6455330 (2002-09-01), Yao et al.
patent: 7927993 (2011-04-01), Kirkpatrick
patent: 2005/0176604 (2005-08-01), Lee et al.
Jeon, J, et al. “Performance of Nitrided Hf Silicate High k Gate Duelectrics.” [online] Advanced Process Development, AMD [retrieved on Dec. 26, 2008] retrieved from the Internet: <www.electrochem.org/dl/ma/203/pdfs/0948.pdf>.

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