High speed pipeline method and apparatus
High speed PLD "AND" array with separate nonvolatile memory
High speed processing flip-flop
High speed product term allocation structure supporting logic it
High speed product term assignment for output enable, clock, inv
High speed programmable address decoder
High speed programmable logic architecture
High speed programmable logic architecture
High speed programmable logic architecture
High speed programmable logic architecture
High speed programmable logic architecture
High speed programmable macrocell with combined path for storage
High speed ratioed CMOS logic structures for a pulsed input envi
High speed receiver with integrated CMOS and PECL capability
High speed receiver with wide input voltage range
High speed reduced area multiplexer
High speed semiconductor circuit having low power consumption
High speed signal driving scheme
High speed signal level converting circuit having a reduced cons
High speed signaling system with adaptive transmit pre-emphasis