I/O architecture/cell design for programmable logic device

I/O block for a programmable interconnect circuit

I/O block for high performance memory interfaces

I/O buffer architecture for programmable devices

I/O buffer circuit with pin multiplexing

I/O buffer circuit with pin multiplexing

I/O buffer having a protection circuit for handling...

I/O buffer power up sequence

I/O buffer with twice the supply voltage tolerance using...

I/O buffer with variable conductivity

I/O cell architecture for CPLDs

I/O cell configuration for multiple I/O standards

I/O cell configuration for multiple I/O standards

I/O cell configuration for multiple I/O standards

I/O cell configuration for multiple I/O standards

I/O circuit with mixed supply voltage capability

I/O circuitry shared between processor and programmable...

I/O circuitry shared between processor and programmable...

I/O circuitry shared between processor and programmable...

I/O driver for integrated circuit with output impedance control